Byte, halfword, and word access in ARM Architecture - Step-by-Step Execution

Concept Flow - Byte, halfword, and word access

Start Access

↓

Determine Access Size

↓

Byte

↓

Calculate Address Offset

↓

Perform Memory Read/Write

↓

Return Data or Store Data

↓

End

The process starts by deciding the size of data to access (byte, halfword, or word), calculates the correct address offset, performs the memory operation, and then returns or stores the data.

Execution Sample

ARM Architecture

LDRB R0, [R1]
LDRH R2, [R1, #2]
LDR  R3, [R1, #4]

Load a byte, a halfword, and a word from memory at different offsets.

Analysis Table

Step	Instruction	Address Accessed	Access Size	Data Loaded/Strored	Notes
1	LDRB R0, [R1]	R1	Byte (8 bits)	Loads 1 byte	Reads 1 byte from address in R1
2	LDRH R2, [R1, #2]	R1 + 2	Halfword (16 bits)	Loads 2 bytes	Reads 2 bytes starting at offset 2
3	LDR R3, [R1, #4]	R1 + 4	Word (32 bits)	Loads 4 bytes	Reads 4 bytes starting at offset 4
4	End	-	-	-	All data loaded according to size and offset

💡 All instructions executed, memory accessed with correct sizes and offsets.

State Tracker

Register	Initial	After Step 1	After Step 2	After Step 3
R0	Unknown	Byte loaded from [R1]	Byte loaded (unchanged)	Byte loaded (unchanged)
R2	Unknown	Unknown	Halfword loaded from [R1+2]	Halfword loaded (unchanged)
R3	Unknown	Unknown	Unknown	Word loaded from [R1+4]
R1	Base address	Base address	Base address	Base address

Key Insights - 3 Insights

Why does LDRB load only 1 byte but LDR loads 4 bytes?

Because LDRB stands for Load Register Byte and accesses 8 bits, while LDR loads a full word of 32 bits. See execution_table steps 1 and 3 for size differences.

What happens if the address is not aligned for halfword or word access?

ARM architecture may raise an alignment fault or handle it differently depending on configuration. The execution_table assumes aligned addresses for halfword and word accesses.

How does the offset affect the memory address accessed?

The offset adds to the base register address to calculate the exact memory location. For example, in step 2, offset #2 means address R1 + 2 bytes.

Visual Quiz - 3 Questions

Look at the execution_table, what size of data does LDRH load at step 2?

A 1 byte

B 2 bytes

C 4 bytes

D 8 bytes

💡 Hint

Check the 'Access Size' column in execution_table row for step 2.

At which step is a full 4-byte word loaded from memory?

A Step 3

B Step 1

C Step 2

D Step 4

💡 Hint

Look at the 'Access Size' and 'Instruction' columns in execution_table.

If the offset in LDRH changed from #2 to #4, what address would it access?

A R1 + 6

B R1 + 2

C R1 + 4

D R1 + 8

💡 Hint

Offsets add to the base address as shown in execution_table step 2.

Concept Snapshot

Byte, halfword, and word access in ARM:
- Byte = 8 bits, halfword = 16 bits, word = 32 bits
- Use LDRB for byte, LDRH for halfword, LDR for word
- Address offset adjusts memory location accessed
- Alignment matters for halfword and word
- Access size determines how many bytes are read or written

Full Transcript

This visual execution shows how ARM instructions access memory in different sizes: byte, halfword, and word. The flow starts by choosing the access size, calculating the address with any offset, performing the memory read or write, and then returning or storing the data. The example code loads a byte, halfword, and word from memory at increasing offsets. The execution table traces each step, showing the instruction, address accessed, size of data, and what is loaded. The variable tracker follows register values after each instruction. Key moments clarify common confusions about size differences, alignment, and address calculation. The quiz tests understanding of data sizes, steps, and address offsets. The snapshot summarizes the key points for quick reference.

Practice

1. What size of data does a halfword represent in ARM architecture?

easy

A. 64 bits

B. 8 bits

C. 32 bits

D. 16 bits

Solution

1. Step 1: Understand data size terms in ARM

   In ARM, a byte is 8 bits, a halfword is twice that size, and a word is 32 bits.

2. Step 2: Identify halfword size

   A halfword is 16 bits because it is two bytes (2 x 8 bits = 16 bits).

3. Final Answer:

   16 bits -> Option D

4. Quick Check:

   Halfword = 16 bits [OK]

Hint: Halfword always means 16 bits or 2 bytes [OK]

Common Mistakes:

• Confusing halfword with byte size
• Thinking halfword is 32 bits
• Mixing halfword with word size

2. Which of the following is the correct ARM instruction syntax to load a single byte from memory into a register?

easy

A. STRB R0, [R1]

B. LDRH R0, [R1]

C. LDRB R0, [R1]

D. LDR R0, [R1]

Solution

1. Step 1: Identify load instructions for different sizes

   In ARM, LDRB loads a byte, LDRH loads a halfword, and LDR loads a word.

2. Step 2: Choose instruction for loading a byte

   LDRB R0, [R1] loads a byte from memory address in R1 into R0.

3. Final Answer:

   LDRB R0, [R1] -> Option C

4. Quick Check:

   LDRB = Load Byte [OK]

Hint: LDRB means load byte, LDRH halfword, LDR word [OK]

Common Mistakes:

• Using LDR instead of LDRB for byte load
• Confusing STRB (store) with load instructions
• Using LDRH which loads 16 bits, not 8

3. Consider the following ARM assembly code snippet:

LDR R0, [R1]
LDRH R2, [R1, #2]
LDRB R3, [R1, #1]

If R1 points to memory starting with bytes 0x12 0x34 0x56 0x78, what will be the value loaded into R2?

medium

A. 0x3456

B. 0x5678

C. 0x7856

D. 0x5634

Solution

1. Step 1: Understand memory layout and addressing

   Memory bytes at R1: 0x12 (offset 0), 0x34 (offset 1), 0x56 (offset 2), 0x78 (offset 3). ARM is little-endian, so lower address holds least significant byte.

2. Step 2: Calculate halfword loaded at offset #2

   Halfword at offset 2 includes bytes at offsets 2 and 3: 0x56 (LSB), 0x78 (MSB). So value is 0x5678.

3. Final Answer:

   0x5678 -> Option B

4. Quick Check:

   Halfword at offset 2 = 0x5678 [OK]

Hint: Remember little-endian: lower address = least significant byte [OK]

Common Mistakes:

• Reading bytes in wrong order (big-endian)
• Using wrong offset for halfword
• Confusing byte and halfword sizes

4. An ARM program tries to load a halfword from an odd memory address using LDRH R0, [R1]. What is the likely problem?

medium

A. Alignment fault or unpredictable behavior

B. It will load a full word instead

C. It will automatically adjust to next even address

D. No problem, halfword loads from any address

Solution

1. Step 1: Understand alignment requirements in ARM

   Halfword accesses must be aligned to even addresses (multiples of 2). Loading from odd addresses causes alignment faults or unpredictable results.

2. Step 2: Identify behavior on misaligned halfword load

   ARM architecture typically raises an alignment fault or behaves unpredictably if halfword is loaded from an odd address.

3. Final Answer:

   Alignment fault or unpredictable behavior -> Option A

4. Quick Check:

   Halfword must be even address [OK]

Hint: Halfword loads require even addresses; odd causes faults [OK]

Common Mistakes:

• Assuming automatic address adjustment
• Thinking halfword loads from any address are safe
• Confusing halfword with byte alignment

5. You need to copy a 32-bit word from an unaligned address in memory to a register in ARM. Which approach correctly handles this situation?

hard

A. Use four byte loads (LDRB) and combine them manually in the register

B. Use a single LDR instruction directly on the unaligned address

C. Use LDRH twice and combine two halfwords

D. Use STR instruction to store the word first, then load it

Solution

1. Step 1: Understand alignment restrictions for word loads

   ARM requires word (32-bit) loads to be aligned to 4-byte boundaries. Unaligned word loads cause faults or incorrect data.

2. Step 2: Choose method to safely load unaligned word

   Loading four bytes individually with LDRB and combining them in the register avoids alignment faults and correctly reconstructs the word.

3. Final Answer:

   Use four byte loads (LDRB) and combine them manually in the register -> Option A

4. Quick Check:

   Unaligned word load = combine bytes manually [OK]

Hint: Unaligned word? Load bytes separately and combine [OK]

Common Mistakes:

• Using single LDR on unaligned address causing faults
• Assuming LDRH twice works for unaligned word
• Misusing STR which stores, not loads