Byte, halfword, and word access in ARM Architecture - Practice Problems & Coding Challenges

Challenge - 5 Problems

🧠 Conceptual

intermediate

Understanding ARM Memory Access Sizes

In ARM architecture, what is the size in bytes of a halfword access?

A 8 bytes

B 1 byte

C 4 bytes

D 2 bytes

💡 Hint

Think about the term 'halfword' as half of a word size in ARM.

A halfword in ARM architecture is 2 bytes because a full word is 4 bytes. Halfword means half of a word.

📋 Factual

intermediate

Word Access Size in ARM

What is the size of a word access in ARM architecture?

A 4 bytes

B 2 bytes

C 1 byte

D 8 bytes

💡 Hint

Recall that ARM is a 32-bit architecture in many common implementations.

A word in ARM architecture is 4 bytes (32 bits). This is the standard size for word access.

🚀 Application

advanced

Effect of Byte Access on Word-Aligned Data

Consider a 32-bit word stored at address 0x1000 in ARM memory. If you perform a byte access at address 0x1002, which byte of the word are you accessing?

A The third byte

B The first (lowest) byte

C The second byte

D The fourth (highest) byte

💡 Hint

Remember that addresses increase by 1 for each byte, and the word starts at 0x1000.

The word at 0x1000 has bytes at 0x1000 (byte 0), 0x1001 (byte 1), 0x1002 (byte 2), and 0x1003 (byte 3). So address 0x1002 accesses the third byte.

🔍 Analysis

advanced

Halfword Access Alignment Requirement

In ARM architecture, what happens if you perform a halfword access at an odd address (e.g., 0x1003)?

A The access succeeds without any penalty

B The processor raises an alignment fault or exception

C The processor automatically aligns the address to the nearest even address

D The access reads two bytes starting from the odd address without issues

💡 Hint

Think about ARM's alignment rules for halfword and word accesses.

ARM requires halfword accesses to be aligned to even addresses. Accessing a halfword at an odd address causes an alignment fault or exception.

❓ Reasoning

expert

Determining Number of Bytes Accessed

You have an ARM instruction that loads a word from memory address 0x2004. How many bytes are read from memory, and what is the address range accessed?

A 1 byte, address 0x2004 only

B 2 bytes, addresses 0x2004 to 0x2005 inclusive

C 4 bytes, addresses 0x2004 to 0x2007 inclusive

D 8 bytes, addresses 0x2004 to 0x200B inclusive

💡 Hint

Recall the size of a word and how addresses increment per byte.

A word in ARM is 4 bytes. Starting at address 0x2004, the bytes accessed are 0x2004, 0x2005, 0x2006, and 0x2007.

Practice

1. What size of data does a halfword represent in ARM architecture?

easy

A. 64 bits

B. 8 bits

C. 32 bits

D. 16 bits

Solution

1. Step 1: Understand data size terms in ARM

   In ARM, a byte is 8 bits, a halfword is twice that size, and a word is 32 bits.

2. Step 2: Identify halfword size

   A halfword is 16 bits because it is two bytes (2 x 8 bits = 16 bits).

3. Final Answer:

   16 bits -> Option D

4. Quick Check:

   Halfword = 16 bits [OK]

Hint: Halfword always means 16 bits or 2 bytes [OK]

Common Mistakes:

• Confusing halfword with byte size
• Thinking halfword is 32 bits
• Mixing halfword with word size

2. Which of the following is the correct ARM instruction syntax to load a single byte from memory into a register?

easy

A. STRB R0, [R1]

B. LDRH R0, [R1]

C. LDRB R0, [R1]

D. LDR R0, [R1]

Solution

1. Step 1: Identify load instructions for different sizes

   In ARM, LDRB loads a byte, LDRH loads a halfword, and LDR loads a word.

2. Step 2: Choose instruction for loading a byte

   LDRB R0, [R1] loads a byte from memory address in R1 into R0.

3. Final Answer:

   LDRB R0, [R1] -> Option C

4. Quick Check:

   LDRB = Load Byte [OK]

Hint: LDRB means load byte, LDRH halfword, LDR word [OK]

Common Mistakes:

• Using LDR instead of LDRB for byte load
• Confusing STRB (store) with load instructions
• Using LDRH which loads 16 bits, not 8

3. Consider the following ARM assembly code snippet:

LDR R0, [R1]
LDRH R2, [R1, #2]
LDRB R3, [R1, #1]

If R1 points to memory starting with bytes 0x12 0x34 0x56 0x78, what will be the value loaded into R2?

medium

A. 0x3456

B. 0x5678

C. 0x7856

D. 0x5634

Solution

1. Step 1: Understand memory layout and addressing

   Memory bytes at R1: 0x12 (offset 0), 0x34 (offset 1), 0x56 (offset 2), 0x78 (offset 3). ARM is little-endian, so lower address holds least significant byte.

2. Step 2: Calculate halfword loaded at offset #2

   Halfword at offset 2 includes bytes at offsets 2 and 3: 0x56 (LSB), 0x78 (MSB). So value is 0x5678.

3. Final Answer:

   0x5678 -> Option B

4. Quick Check:

   Halfword at offset 2 = 0x5678 [OK]

Hint: Remember little-endian: lower address = least significant byte [OK]

Common Mistakes:

• Reading bytes in wrong order (big-endian)
• Using wrong offset for halfword
• Confusing byte and halfword sizes

4. An ARM program tries to load a halfword from an odd memory address using LDRH R0, [R1]. What is the likely problem?

medium

A. Alignment fault or unpredictable behavior

B. It will load a full word instead

C. It will automatically adjust to next even address

D. No problem, halfword loads from any address

Solution

1. Step 1: Understand alignment requirements in ARM

   Halfword accesses must be aligned to even addresses (multiples of 2). Loading from odd addresses causes alignment faults or unpredictable results.

2. Step 2: Identify behavior on misaligned halfword load

   ARM architecture typically raises an alignment fault or behaves unpredictably if halfword is loaded from an odd address.

3. Final Answer:

   Alignment fault or unpredictable behavior -> Option A

4. Quick Check:

   Halfword must be even address [OK]

Hint: Halfword loads require even addresses; odd causes faults [OK]

Common Mistakes:

• Assuming automatic address adjustment
• Thinking halfword loads from any address are safe
• Confusing halfword with byte alignment

5. You need to copy a 32-bit word from an unaligned address in memory to a register in ARM. Which approach correctly handles this situation?

hard

A. Use four byte loads (LDRB) and combine them manually in the register

B. Use a single LDR instruction directly on the unaligned address

C. Use LDRH twice and combine two halfwords

D. Use STR instruction to store the word first, then load it

Solution

1. Step 1: Understand alignment restrictions for word loads

   ARM requires word (32-bit) loads to be aligned to 4-byte boundaries. Unaligned word loads cause faults or incorrect data.

2. Step 2: Choose method to safely load unaligned word

   Loading four bytes individually with LDRB and combining them in the register avoids alignment faults and correctly reconstructs the word.

3. Final Answer:

   Use four byte loads (LDRB) and combine them manually in the register -> Option A

4. Quick Check:

   Unaligned word load = combine bytes manually [OK]

Hint: Unaligned word? Load bytes separately and combine [OK]

Common Mistakes:

• Using single LDR on unaligned address causing faults
• Assuming LDRH twice works for unaligned word
• Misusing STR which stores, not loads