Byte, halfword, and word access in ARM Architecture - Mini Project: Build & Apply

Byte, halfword, and word access

📖 Scenario: You are learning how data is accessed in ARM processors. Data can be read or written in different sizes: bytes (8 bits), halfwords (16 bits), and words (32 bits). Understanding how to access these sizes correctly is important for working with memory and registers.

🎯 Goal: Build a simple example showing how to define memory data and access it as bytes, halfwords, and words in ARM assembly style pseudocode.

📋 What You'll Learn

Create a memory array with 4 bytes of data

Define variables for byte, halfword, and word access

Use correct indexing to access the byte, halfword, and word

Show the final memory access instructions with correct sizes

💡 Why This Matters

🌍 Real World

Understanding byte, halfword, and word access is essential when working with low-level programming, embedded systems, or debugging memory in ARM-based devices.

💼 Career

This knowledge is important for embedded software developers, firmware engineers, and anyone working with ARM architecture or hardware interfacing.

1

Create a memory array with 4 bytes

Create a variable called memory that holds exactly these 4 bytes: 0x12, 0x34, 0x56, and 0x78.

ARM Architecture

# Create the memory array with 4 bytes
# Your code here

Hint

Use a list to represent the memory bytes in order.

2

Define variables for byte, halfword, and word indices

Create three variables: byte_index set to 1, halfword_index set to 1, and word_index set to 0 to represent the starting positions for each access size.

ARM Architecture

memory = [0x12, 0x34, 0x56, 0x78]
# Define indices for byte, halfword, and word access
# Your code here

Hint

Indices represent the starting byte position in the memory list.

3

Access the byte, halfword, and word from memory

Create three variables: byte_value to hold the byte at byte_index, halfword_value to hold the 16-bit halfword starting at halfword_index, and word_value to hold the 32-bit word starting at word_index. Combine bytes in little-endian order (lowest address is least significant byte).

ARM Architecture

memory = [0x12, 0x34, 0x56, 0x78]
byte_index = 1
halfword_index = 1
word_index = 0
# Access byte, halfword, and word values
# Your code here

Hint

Use bitwise OR and shifts to combine bytes in little-endian order.

4

Show the final memory access instructions

Add comments explaining each access: byte_value is the single byte at index 1, halfword_value is the 16-bit value from bytes 1 and 2, and word_value is the 32-bit value from bytes 0 to 3.

ARM Architecture

memory = [0x12, 0x34, 0x56, 0x78]
byte_index = 1
halfword_index = 1
word_index = 0
byte_value = memory[byte_index]
halfword_value = memory[halfword_index] | (memory[halfword_index + 1] << 8)
word_value = (memory[word_index] |
              (memory[word_index + 1] << 8) |
              (memory[word_index + 2] << 16) |
              (memory[word_index + 3] << 24))
# Add comments explaining each access
# Your code here

Hint

Comments help explain what each variable represents in memory access.

Practice

1. What size of data does a halfword represent in ARM architecture?

easy

A. 64 bits

B. 8 bits

C. 32 bits

D. 16 bits

Solution

1. Step 1: Understand data size terms in ARM

   In ARM, a byte is 8 bits, a halfword is twice that size, and a word is 32 bits.

2. Step 2: Identify halfword size

   A halfword is 16 bits because it is two bytes (2 x 8 bits = 16 bits).

3. Final Answer:

   16 bits -> Option D

4. Quick Check:

   Halfword = 16 bits [OK]

Hint: Halfword always means 16 bits or 2 bytes [OK]

Common Mistakes:

• Confusing halfword with byte size
• Thinking halfword is 32 bits
• Mixing halfword with word size

2. Which of the following is the correct ARM instruction syntax to load a single byte from memory into a register?

easy

A. STRB R0, [R1]

B. LDRH R0, [R1]

C. LDRB R0, [R1]

D. LDR R0, [R1]

Solution

1. Step 1: Identify load instructions for different sizes

   In ARM, LDRB loads a byte, LDRH loads a halfword, and LDR loads a word.

2. Step 2: Choose instruction for loading a byte

   LDRB R0, [R1] loads a byte from memory address in R1 into R0.

3. Final Answer:

   LDRB R0, [R1] -> Option C

4. Quick Check:

   LDRB = Load Byte [OK]

Hint: LDRB means load byte, LDRH halfword, LDR word [OK]

Common Mistakes:

• Using LDR instead of LDRB for byte load
• Confusing STRB (store) with load instructions
• Using LDRH which loads 16 bits, not 8

3. Consider the following ARM assembly code snippet:

LDR R0, [R1]
LDRH R2, [R1, #2]
LDRB R3, [R1, #1]

If R1 points to memory starting with bytes 0x12 0x34 0x56 0x78, what will be the value loaded into R2?

medium

A. 0x3456

B. 0x5678

C. 0x7856

D. 0x5634

Solution

1. Step 1: Understand memory layout and addressing

   Memory bytes at R1: 0x12 (offset 0), 0x34 (offset 1), 0x56 (offset 2), 0x78 (offset 3). ARM is little-endian, so lower address holds least significant byte.

2. Step 2: Calculate halfword loaded at offset #2

   Halfword at offset 2 includes bytes at offsets 2 and 3: 0x56 (LSB), 0x78 (MSB). So value is 0x5678.

3. Final Answer:

   0x5678 -> Option B

4. Quick Check:

   Halfword at offset 2 = 0x5678 [OK]

Hint: Remember little-endian: lower address = least significant byte [OK]

Common Mistakes:

• Reading bytes in wrong order (big-endian)
• Using wrong offset for halfword
• Confusing byte and halfword sizes

4. An ARM program tries to load a halfword from an odd memory address using LDRH R0, [R1]. What is the likely problem?

medium

A. Alignment fault or unpredictable behavior

B. It will load a full word instead

C. It will automatically adjust to next even address

D. No problem, halfword loads from any address

Solution

1. Step 1: Understand alignment requirements in ARM

   Halfword accesses must be aligned to even addresses (multiples of 2). Loading from odd addresses causes alignment faults or unpredictable results.

2. Step 2: Identify behavior on misaligned halfword load

   ARM architecture typically raises an alignment fault or behaves unpredictably if halfword is loaded from an odd address.

3. Final Answer:

   Alignment fault or unpredictable behavior -> Option A

4. Quick Check:

   Halfword must be even address [OK]

Hint: Halfword loads require even addresses; odd causes faults [OK]

Common Mistakes:

• Assuming automatic address adjustment
• Thinking halfword loads from any address are safe
• Confusing halfword with byte alignment

5. You need to copy a 32-bit word from an unaligned address in memory to a register in ARM. Which approach correctly handles this situation?

hard

A. Use four byte loads (LDRB) and combine them manually in the register

B. Use a single LDR instruction directly on the unaligned address

C. Use LDRH twice and combine two halfwords

D. Use STR instruction to store the word first, then load it

Solution

1. Step 1: Understand alignment restrictions for word loads

   ARM requires word (32-bit) loads to be aligned to 4-byte boundaries. Unaligned word loads cause faults or incorrect data.

2. Step 2: Choose method to safely load unaligned word

   Loading four bytes individually with LDRB and combining them in the register avoids alignment faults and correctly reconstructs the word.

3. Final Answer:

   Use four byte loads (LDRB) and combine them manually in the register -> Option A

4. Quick Check:

   Unaligned word load = combine bytes manually [OK]

Hint: Unaligned word? Load bytes separately and combine [OK]

Common Mistakes:

• Using single LDR on unaligned address causing faults
• Assuming LDRH twice works for unaligned word
• Misusing STR which stores, not loads