Route planning for two-layer board in PCB Design - Real Business Scenario

Scenario Mode

👤 Your Role: You are a PCB design engineer working on a two-layer printed circuit board.

📋 Request: Your manager wants you to plan the routing of signals on the two-layer board to optimize space and minimize interference.

📊 Data: You have a list of components with their pin locations on the top and bottom layers, and the netlist showing which pins need to be connected.

🎯 Deliverable: Create a routing plan that shows which signals go on the top layer and which go on the bottom layer, with a visualization of the routing paths.

Sample Data

Component	Pin	Layer	X (mm)	Y (mm)	Net
U1	1	Top	10	10	NET_A
U1	2	Top	12	10	NET_B
R1	1	Bottom	15	15	NET_A
R1	2	Bottom	17	15	NET_C
C1	1	Top	20	10	NET_B
C1	2	Top	22	10	NET_C
U2	1	Bottom	25	20	NET_D
U2	2	Bottom	27	20	NET_E
R2	1	Top	30	25	NET_D
R2	2	Top	32	25	NET_E

1

Step 1: Organize the netlist by grouping pins that share the same net to identify connections.

Group data by 'Net' column to list all pins and their layers for each net.

Expected Result

NET_A: U1 Pin1 (Top), R1 Pin1 (Bottom); NET_B: U1 Pin2 (Top), C1 Pin1 (Top); NET_C: R1 Pin2 (Bottom), C1 Pin2 (Top); NET_D: U2 Pin1 (Bottom), R2 Pin1 (Top); NET_E: U2 Pin2 (Bottom), R2 Pin2 (Top)

2

Step 2: Assign routing layers for each net to minimize layer changes and avoid crossing signals.

For nets with pins on both layers, assign the net to the layer with majority pins or use vias to connect layers.

Expected Result

NET_A routed on both layers with via; NET_B routed on Top layer; NET_C routed on both layers with via; NET_D routed on both layers with via; NET_E routed on both layers with via

3

Step 3: Plan routing paths by connecting pins on assigned layers using shortest paths avoiding overlaps.

Use Manhattan distance routing between pin coordinates on assigned layers, ensuring no crossing paths on the same layer.

Expected Result

NET_B routed from U1 Pin2 (12,10) to C1 Pin1 (20,10) on Top layer; NET_A routed from U1 Pin1 (10,10) to via, then via to R1 Pin1 (15,15) on Bottom layer; similarly for other nets.

4

Step 4: Create a visualization showing the top and bottom layers with routing paths and vias.

Draw two separate layer maps with component pins and routing lines; mark vias where layer changes occur.

Expected Result

Top layer map shows NET_B and parts of NET_C, NET_D, NET_E; Bottom layer map shows NET_A and parts of NET_C, NET_D, NET_E; vias marked at layer change points.

5

Step 5: Review routing plan for signal integrity and space optimization.

Check for minimal crossing, shortest path usage, and balanced layer usage.

Expected Result

Routing plan uses both layers efficiently, minimizes vias, and avoids signal interference.

Final Result

Top Layer Routing:
U1(12,10)---NET_B---C1(20,10)   R2(32,25)---NET_E---U2(27,20)
|                 |             |
NET_C via          |             |
Bottom Layer Routing:
R1(15,15)---NET_A---U1(10,10)   U2(25,20)---NET_D---R2(30,25)
|                 |
NET_C via

Vias connect nets between layers at strategic points.

✓Routing on two layers reduces congestion and allows efficient use of board space.

✓Using vias strategically connects signals between layers without excessive complexity.

✓Assigning nets to layers based on pin locations minimizes unnecessary layer changes.

Bonus Challenge

Optimize the routing plan to reduce the number of vias by reassigning nets to layers where possible.

Show Hint

Analyze nets with pins on both layers and consider moving some connections entirely to one layer if space allows.

Practice

1. What is the main advantage of using two layers in PCB route planning?

easy

A. Separating signals and power to reduce interference

B. Making the board heavier

C. Increasing the number of components

D. Reducing the cost of materials

Solution

1. Step 1: Understand layer usage in PCB design

   Two layers allow separating signal traces and power/ground planes, which reduces electrical noise and interference.

2. Step 2: Identify the benefit of separation

   Separating signals and power improves signal integrity and reduces crosstalk between traces.

3. Final Answer:

   Separating signals and power to reduce interference -> Option A

4. Quick Check:

   Two layers separate signals and power [OK]

Hint: Two layers separate signals and power for less noise [OK]

Common Mistakes:

• Thinking two layers just add weight
• Assuming more components fit automatically
• Believing cost always decreases with two layers

2. Which of the following is the correct way to represent a via connecting top and bottom layers in a PCB design file?

easy

A. via(top-bottom)

B. via(top, bottom)

C. via(top_layer, bottom_layer)

D. via(top;bottom)

Solution

1. Step 1: Review correct syntax for via definition

   In PCB design files, vias are typically defined with two layers separated by a comma inside parentheses.

2. Step 2: Identify the correct syntax among options

   via(top_layer, bottom_layer) uses via(top_layer, bottom_layer) which is the standard and syntactically correct format.

3. Final Answer:

   <code>via(top_layer, bottom_layer)</code> -> Option C

4. Quick Check:

   Via syntax uses comma between layers [OK]

Hint: Use comma to separate layers in via syntax [OK]

Common Mistakes:

• Using hyphens or semicolons instead of commas
• Missing parentheses around layers
• Incorrect layer names or casing

3. Given the following route plan code snippet, what is the total number of vias used?

routes = [
  {"start": "A", "end": "B", "layer": "top"},
  {"start": "B", "end": "C", "layer": "bottom"},
  {"start": "C", "end": "D", "layer": "top"}
]
vias = [route for route in routes if route["layer"] != routes[routes.index(route)-1]["layer"]]
print(len(vias))

medium

A. 0

B. 2

C. 1

D. 3

Solution

1. Step 1: Analyze the route layers sequence

   The layers are: top (A-B), bottom (B-C), top (C-D). Changes occur from top to bottom and bottom to top.

2. Step 2: Count layer changes indicating vias

   There are two layer changes: top to bottom and bottom to top, so two vias are needed.

3. Final Answer:

   2 -> Option B

4. Quick Check:

   Layer changes = number of vias = 2 [OK]

Hint: Count layer switches to find vias needed [OK]

Common Mistakes:

• Counting all routes as vias
• Ignoring first route layer
• Misreading layer sequence

4. You have this route planning code snippet that throws an error:

routes = [
  {"start": "X", "end": "Y", "layer": "top"},
  {"start": "Y", "end": "Z", "layer": "bottom"}
]
vias = [route for i, route in enumerate(routes) if route["layer"] != routes[i-1]["layer"]]
print(len(vias))

What is the cause of the error?

medium

A. Index -1 is invalid for the first element

B. Missing parentheses in list comprehension

C. Incorrect key name in route dictionary

D. Using enumerate without unpacking

Solution

1. Step 1: Identify the error cause in list comprehension

   The code accesses routes[i-1] even when i=0, causing routes[-1] which is valid in Python but may cause logic error if unintended.

2. Step 2: Understand Python negative index behavior

   Python allows negative indices, so routes[-1] accesses last element, causing incorrect comparison and logic error, not runtime error.

3. Step 3: Check if error is runtime or logic

   Since no runtime error occurs, the problem is logic error due to comparing first element with last element incorrectly.

4. Final Answer:

   Index -1 is invalid for the first element -> Option A

5. Quick Check:

   Negative index causes wrong comparison [OK]

Hint: Watch out for negative indices in loops [OK]

Common Mistakes:

• Assuming negative index causes runtime error
• Ignoring logic error from wrong comparison
• Confusing enumerate unpacking syntax

5. You need to plan routes on a two-layer PCB to connect points A, B, C, and D with minimal vias. The connections are A-B, B-C, and C-D. Which routing strategy best reduces vias?

hard

A. Route A-B and B-C on top, C-D on bottom layer

B. Alternate layers for each connection to balance load

C. Route A-B on bottom, B-C and C-D on top

D. Route all connections on the top layer only

Solution

1. Step 1: Understand via usage in layer changes

   Each time a route switches layers, a via is needed, increasing complexity and cost.

2. Step 2: Analyze options for minimal vias

   Routing all connections on the same layer (top) avoids layer switching and thus uses zero vias.

3. Step 3: Compare other options

   Alternating or mixing layers causes at least one via for each layer change, increasing vias count.

4. Final Answer:

   Route all connections on the top layer only -> Option D

5. Quick Check:

   Same layer routing means zero vias [OK]

Hint: Keep routes on one layer to avoid vias [OK]

Common Mistakes:

• Thinking alternating layers reduce vias
• Ignoring that each layer change needs a via
• Assuming balancing load is more important than vias