Route planning for two-layer board in PCB Design - Real Business Scenario

Scenario Mode

👤 Your Role: You are a PCB design engineer working on a two-layer printed circuit board.

📋 Request: Your manager wants you to plan the routing of signals on the two-layer board to optimize space and minimize interference.

📊 Data: You have a list of components with their pin locations on the top and bottom layers, and the netlist showing which pins need to be connected.

🎯 Deliverable: Create a routing plan that shows which signals go on the top layer and which go on the bottom layer, with a visualization of the routing paths.

Sample Data

Component	Pin	Layer	X (mm)	Y (mm)	Net
U1	1	Top	10	10	NET_A
U1	2	Top	12	10	NET_B
R1	1	Bottom	15	15	NET_A
R1	2	Bottom	17	15	NET_C
C1	1	Top	20	10	NET_B
C1	2	Top	22	10	NET_C
U2	1	Bottom	25	20	NET_D
U2	2	Bottom	27	20	NET_E
R2	1	Top	30	25	NET_D
R2	2	Top	32	25	NET_E

1

Step 1: Organize the netlist by grouping pins that share the same net to identify connections.

Group data by 'Net' column to list all pins and their layers for each net.

Expected Result

NET_A: U1 Pin1 (Top), R1 Pin1 (Bottom); NET_B: U1 Pin2 (Top), C1 Pin1 (Top); NET_C: R1 Pin2 (Bottom), C1 Pin2 (Top); NET_D: U2 Pin1 (Bottom), R2 Pin1 (Top); NET_E: U2 Pin2 (Bottom), R2 Pin2 (Top)

2

Step 2: Assign routing layers for each net to minimize layer changes and avoid crossing signals.

For nets with pins on both layers, assign the net to the layer with majority pins or use vias to connect layers.

Expected Result

NET_A routed on both layers with via; NET_B routed on Top layer; NET_C routed on both layers with via; NET_D routed on both layers with via; NET_E routed on both layers with via

3

Step 3: Plan routing paths by connecting pins on assigned layers using shortest paths avoiding overlaps.

Use Manhattan distance routing between pin coordinates on assigned layers, ensuring no crossing paths on the same layer.

Expected Result

NET_B routed from U1 Pin2 (12,10) to C1 Pin1 (20,10) on Top layer; NET_A routed from U1 Pin1 (10,10) to via, then via to R1 Pin1 (15,15) on Bottom layer; similarly for other nets.

4

Step 4: Create a visualization showing the top and bottom layers with routing paths and vias.

Draw two separate layer maps with component pins and routing lines; mark vias where layer changes occur.

Expected Result

Top layer map shows NET_B and parts of NET_C, NET_D, NET_E; Bottom layer map shows NET_A and parts of NET_C, NET_D, NET_E; vias marked at layer change points.

5

Step 5: Review routing plan for signal integrity and space optimization.

Check for minimal crossing, shortest path usage, and balanced layer usage.

Expected Result

Routing plan uses both layers efficiently, minimizes vias, and avoids signal interference.

Final Result

Top Layer Routing:
U1(12,10)---NET_B---C1(20,10)   R2(32,25)---NET_E---U2(27,20)
|                 |             |
NET_C via          |             |
Bottom Layer Routing:
R1(15,15)---NET_A---U1(10,10)   U2(25,20)---NET_D---R2(30,25)
|                 |
NET_C via

Vias connect nets between layers at strategic points.

✓Routing on two layers reduces congestion and allows efficient use of board space.

✓Using vias strategically connects signals between layers without excessive complexity.

✓Assigning nets to layers based on pin locations minimizes unnecessary layer changes.

Bonus Challenge

Optimize the routing plan to reduce the number of vias by reassigning nets to layers where possible.

Show Hint

Analyze nets with pins on both layers and consider moving some connections entirely to one layer if space allows.