Interrupt priority levels in Embedded C - Step-by-Step Execution

Concept Flow - Interrupt priority levels

Interrupt Occurs

↓

Check Current CPU State

↓

Compare Interrupt Priority

↓

Preempt

↓

Execute ISR

↓

Return to Main or Lower ISR

When an interrupt happens, the CPU checks if its priority is higher than the current task. If yes, it pauses the current task and runs the interrupt. Otherwise, it waits.

Execution Sample

Embedded C

void ISR1() {
  // Priority 2
  // Handle interrupt
}

void ISR2() {
  // Priority 1
  // Handle interrupt
}

Two interrupt service routines (ISRs) with different priorities; ISR2 has higher priority than ISR1.

Execution Table

Step	Event	Current CPU State	Interrupt Priority	Action Taken	Result
1	ISR1 interrupt occurs	Idle	2	Start ISR1	ISR1 runs
2	ISR2 interrupt occurs	ISR1 running (priority 2)	1	Preempt ISR1	ISR2 runs
3	ISR2 completes	ISR2 running	N/A	Return to ISR1	ISR1 resumes
4	ISR1 completes	ISR1 running	N/A	Return to main	CPU idle
5	No more interrupts	CPU idle	N/A	Wait	Idle state maintained

💡 No more interrupts; CPU returns to idle state.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
CPU State	Idle	ISR1 running	ISR2 running	ISR1 running	Idle	Idle
Current Interrupt	None	ISR1	ISR2	ISR1	None	None

Key Moments - 2 Insights

Why does ISR2 preempt ISR1 even though ISR1 started first?

Because ISR2 has a higher priority (1 is higher than 2), it interrupts ISR1. See execution_table step 2 where ISR2 preempts ISR1.

What happens if an interrupt with lower or equal priority occurs during another ISR?

It waits until the current ISR finishes. This is shown in the flow where lower or equal priority interrupts do not preempt.

Visual Quiz - 3 Questions

Look at the execution_table at step 2, what is the CPU state after ISR2 interrupt occurs?

A ISR1 running

B ISR2 running

C Idle

D Main program running

💡 Hint

Check the 'Current CPU State' and 'Result' columns at step 2 in execution_table.

At which step does the CPU return to idle state?

A Step 3

B Step 5

C Step 4

D Step 1

💡 Hint

Look at the 'CPU State' variable in variable_tracker after step 4.

If ISR2 had priority 3 instead of 1, what would happen at step 2?

A ISR2 would wait until ISR1 finishes

B ISR1 would stop and ISR2 would run simultaneously

C ISR2 would preempt ISR1

D CPU would crash

💡 Hint

Recall that lower priority interrupts do not preempt higher priority ones, see concept_flow.

Concept Snapshot

Interrupt Priority Levels:
- Higher priority interrupts can pause lower priority tasks.
- CPU checks priority before switching.
- Equal or lower priority interrupts wait.
- Helps manage multiple interrupts efficiently.

Full Transcript

This visual trace shows how interrupt priority levels control which interrupt runs first. When ISR1 with priority 2 starts, the CPU runs it. Then ISR2 with higher priority 1 occurs and preempts ISR1. After ISR2 finishes, ISR1 resumes and completes. Finally, CPU returns to idle. Lower priority interrupts wait until higher priority ones finish. This system ensures urgent tasks get immediate attention.