Interrupt priority levels in Embedded C - Step-by-Step Execution

Concept Flow - Interrupt priority levels

Interrupt Occurs

↓

Check Current CPU State

↓

Compare Interrupt Priority

↓

Preempt

↓

Execute ISR

↓

Return to Main or Lower ISR

When an interrupt happens, the CPU checks if its priority is higher than the current task. If yes, it pauses the current task and runs the interrupt. Otherwise, it waits.

Execution Sample

Embedded C

void ISR1() {
  // Priority 2
  // Handle interrupt
}

void ISR2() {
  // Priority 1
  // Handle interrupt
}

Two interrupt service routines (ISRs) with different priorities; ISR2 has higher priority than ISR1.

Execution Table

Step	Event	Current CPU State	Interrupt Priority	Action Taken	Result
1	ISR1 interrupt occurs	Idle	2	Start ISR1	ISR1 runs
2	ISR2 interrupt occurs	ISR1 running (priority 2)	1	Preempt ISR1	ISR2 runs
3	ISR2 completes	ISR2 running	N/A	Return to ISR1	ISR1 resumes
4	ISR1 completes	ISR1 running	N/A	Return to main	CPU idle
5	No more interrupts	CPU idle	N/A	Wait	Idle state maintained

💡 No more interrupts; CPU returns to idle state.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
CPU State	Idle	ISR1 running	ISR2 running	ISR1 running	Idle	Idle
Current Interrupt	None	ISR1	ISR2	ISR1	None	None

Key Moments - 2 Insights

Why does ISR2 preempt ISR1 even though ISR1 started first?

Because ISR2 has a higher priority (1 is higher than 2), it interrupts ISR1. See execution_table step 2 where ISR2 preempts ISR1.

What happens if an interrupt with lower or equal priority occurs during another ISR?

It waits until the current ISR finishes. This is shown in the flow where lower or equal priority interrupts do not preempt.

Visual Quiz - 3 Questions

Look at the execution_table at step 2, what is the CPU state after ISR2 interrupt occurs?

A ISR1 running

B ISR2 running

C Idle

D Main program running

💡 Hint

Check the 'Current CPU State' and 'Result' columns at step 2 in execution_table.

At which step does the CPU return to idle state?

A Step 3

B Step 5

C Step 4

D Step 1

💡 Hint

Look at the 'CPU State' variable in variable_tracker after step 4.

If ISR2 had priority 3 instead of 1, what would happen at step 2?

A ISR2 would wait until ISR1 finishes

B ISR1 would stop and ISR2 would run simultaneously

C ISR2 would preempt ISR1

D CPU would crash

💡 Hint

Recall that lower priority interrupts do not preempt higher priority ones, see concept_flow.

Concept Snapshot

Interrupt Priority Levels:
- Higher priority interrupts can pause lower priority tasks.
- CPU checks priority before switching.
- Equal or lower priority interrupts wait.
- Helps manage multiple interrupts efficiently.

Full Transcript

This visual trace shows how interrupt priority levels control which interrupt runs first. When ISR1 with priority 2 starts, the CPU runs it. Then ISR2 with higher priority 1 occurs and preempts ISR1. After ISR2 finishes, ISR1 resumes and completes. Finally, CPU returns to idle. Lower priority interrupts wait until higher priority ones finish. This system ensures urgent tasks get immediate attention.

Practice

1.

What does a lower interrupt priority number mean in embedded C?

easy

A. It has lower priority and runs after others

B. It disables all other interrupts

C. It has higher priority and runs before others

D. It runs only when the CPU is idle

Solution

1. Step 1: Understand priority numbering

   In embedded C, interrupt priority levels are numbered so that lower numbers mean higher priority.

2. Step 2: Interpret priority effect

   Therefore, an interrupt with a lower number runs before interrupts with higher numbers.

3. Final Answer:

   It has higher priority and runs before others -> Option C

4. Quick Check:

   Lower number = higher priority [OK]

Hint: Lower number means higher priority, runs first [OK]

Common Mistakes:

• Thinking higher number means higher priority
• Confusing priority with interrupt enable/disable
• Assuming priority affects CPU idle time

2.

Which of the following is the correct way to set an interrupt priority level to 2 in embedded C?

void setup_interrupt() {
    // Set priority here
}

easy

A. NVIC_SetPriority(IRQn, HIGH);

B. NVIC_SetPriority(IRQn, 2);

C. NVIC_EnableIRQ(2);

D. NVIC_SetPriority(IRQn, 10);

Solution

1. Step 1: Identify correct function to set priority

   NVIC_SetPriority is the standard function to set interrupt priority in embedded C.

2. Step 2: Check correct priority value

   Passing 2 as the priority sets the interrupt priority level to 2 correctly.

3. Final Answer:

   NVIC_SetPriority(IRQn, 2); -> Option B

4. Quick Check:

   Use NVIC_SetPriority with numeric level [OK]

Hint: Use NVIC_SetPriority with number for priority [OK]

Common Mistakes:

• Using NVIC_EnableIRQ to set priority
• Passing symbolic constants instead of numbers
• Setting priority to a value outside allowed range

3.

Given the following code snippet, what will be the order of interrupt execution if both interrupts occur simultaneously?

NVIC_SetPriority(IRQn_UART, 3);
NVIC_SetPriority(IRQn_TIMER, 1);
// Both UART and TIMER interrupts triggered at the same time

medium

A. TIMER interrupt runs first, then UART

B. Both run simultaneously

C. UART interrupt runs first, then TIMER

D. No interrupt runs due to conflict

Solution

1. Step 1: Identify priority levels assigned

   UART interrupt priority is set to 3, TIMER interrupt priority is set to 1.

2. Step 2: Determine which priority is higher

   Lower number means higher priority, so TIMER (1) runs before UART (3).

3. Final Answer:

   TIMER interrupt runs first, then UART -> Option A

4. Quick Check:

   Lower priority number runs first [OK]

Hint: Lower priority number runs before higher [OK]

Common Mistakes:

• Assuming higher number runs first
• Thinking interrupts run simultaneously
• Ignoring priority settings

4.

Identify the error in this code snippet that sets interrupt priorities:

NVIC_SetPriority(IRQn_ADC, 5);
NVIC_SetPriority(IRQn_ADC, 0);
NVIC_EnableIRQ(IRQn_ADC);

What is the problem?

medium

A. Priority 0 is invalid and causes error

B. Setting priority twice causes conflict

C. No error, code works fine

D. Priority 0 is higher than priority 5, so last setting wins

Solution

1. Step 1: Analyze priority assignments

   The code sets priority 5 first, then overwrites it with priority 0 for the same interrupt.

2. Step 2: Understand priority effect

   Priority 0 is higher priority than 5, so the last setting (0) is effective.

3. Final Answer:

   Priority 0 is higher than priority 5, so last setting wins -> Option D

4. Quick Check:

   Last priority set is used [OK]

Hint: Last priority set is effective [OK]

Common Mistakes:

• Thinking priority 0 is invalid
• Assuming multiple priorities combine
• Ignoring order of calls

5.

You have three interrupts: IRQn_A, IRQn_B, and IRQn_C. You want IRQn_B to run first, then IRQn_C, and finally IRQn_A. Which priority settings achieve this?

hard

A. IRQn_B = 1, IRQn_C = 2, IRQn_A = 3

B. IRQn_A = 1, IRQn_B = 2, IRQn_C = 3

C. IRQn_C = 1, IRQn_A = 2, IRQn_B = 3

D. IRQn_B = 3, IRQn_C = 2, IRQn_A = 1

Solution

1. Step 1: Understand priority order needed

   IRQn_B should run first, then IRQn_C, then IRQn_A last.

2. Step 2: Assign priorities accordingly

   Lower number means higher priority, so IRQn_B = 1, IRQn_C = 2, IRQn_A = 3 matches the desired order.

3. Final Answer:

   IRQn_B = 1, IRQn_C = 2, IRQn_A = 3 -> Option A

4. Quick Check:

   Lower number runs first [OK]

Hint: Assign lower numbers to interrupts needing higher priority [OK]

Common Mistakes:

• Assigning higher numbers for higher priority
• Mixing up interrupt names and priorities
• Not following the required order