I2C bus architecture (SDA, SCL) in Embedded C - Step-by-Step Execution

Concept Flow - I2C bus architecture (SDA, SCL)

Start Condition

↓

Master sends clock on SCL

↓

Master sends data bit on SDA

↓

Slave reads data bit on SDA

↓

Master waits for ACK from Slave

↓

Repeat for all bits

↓

Stop Condition

The I2C bus uses two lines: SDA for data and SCL for clock. The master controls the clock and data bits, and the slave responds with acknowledgments.

Execution Sample

Embedded C

void i2c_write_bit(int bit) {
  set_SDA(bit);       // Set data line
  set_SCL(1);        // Clock high
  delay();           // Wait
  set_SCL(0);        // Clock low
}

This code sends one bit on the I2C bus by setting SDA and toggling SCL.

Execution Table

Step	SCL (Clock)	SDA (Data)	Action	Result
1	0	Start (High)	Start Condition: SDA goes low while SCL is high	Bus ready for data
2	0->1	1	Set SDA to 1, then SCL high	Data bit 1 sent
3	1->0	1	SCL goes low	Prepare for next bit
4	0->1	0	Set SDA to 0, then SCL high	Data bit 0 sent
5	1->0	0	SCL goes low	Prepare for next bit
6	0->1	ACK (Slave pulls SDA low)	Slave acknowledges	Master receives ACK
7	1->0	ACK	SCL goes low	Ready for next byte or stop
8	1	Stop (Low->High)	Stop Condition: SDA goes high while SCL is high	Bus released

💡 Stop condition ends communication, SDA and SCL return to idle high state

Variable Tracker

Signal Line	Start	After Step 2	After Step 4	After Step 6	After Step 8
SCL	1 (idle)	1	1	1	1 (idle)
SDA	1 (idle)	1	0	0 (ACK low)	1 (idle)

Key Moments - 2 Insights

Why does SDA change only when SCL is low except for start and stop?

Because data bits on SDA must be stable when SCL is high to be read correctly. This is shown in steps 2 and 4 where SDA changes before SCL goes high.

What is the purpose of the ACK bit from the slave?

The ACK bit (step 6) lets the master know the slave received the data. The slave pulls SDA low during SCL high to acknowledge.

Visual Quiz - 3 Questions

Look at the execution table, what is the state of SDA during step 4?

A High (1)

B Low (0)

C Floating

D Toggling

💡 Hint

Check the SDA column in row for step 4 in the execution_table

At which step does the slave send an acknowledgment?

A Step 2

B Step 4

C Step 6

D Step 8

💡 Hint

Look for the ACK action in the execution_table rows

If SDA changed while SCL was high during data bits, what would happen?

A Data would be read incorrectly

B Communication would speed up

C Slave would send NACK

D Nothing changes

💡 Hint

Refer to key_moments about SDA stability during SCL high

Concept Snapshot

I2C uses two lines: SDA (data) and SCL (clock).
Master controls SCL and sets SDA bits.
Data bits must be stable when SCL is high.
Start: SDA falls while SCL high.
Stop: SDA rises while SCL high.
Slave ACKs by pulling SDA low during SCL high.

Full Transcript

The I2C bus architecture uses two wires: SDA for data and SCL for clock. Communication starts with a start condition where SDA goes low while SCL is high. The master sends data bits by setting SDA and toggling SCL. Data bits must be stable when SCL is high so the slave can read them correctly. After each byte, the slave sends an acknowledgment by pulling SDA low during the clock pulse. Communication ends with a stop condition where SDA goes high while SCL is high. This ensures clear signaling and synchronization between master and slave devices on the bus.

Practice

1. Which two lines are used in the I2C bus architecture for communication?

easy

A. CLK for data and DAT for clock

B. TX for data and RX for clock

C. SDA for data and SCL for clock

D. MOSI for data and MISO for clock

Solution

1. Step 1: Recall I2C bus lines

   I2C uses two specific lines: SDA and SCL.

2. Step 2: Identify roles of lines

   SDA carries data, and SCL carries the clock signal.

3. Final Answer:

   SDA for data and SCL for clock -> Option C

4. Quick Check:

   I2C lines = SDA + SCL [OK]

Hint: Remember: SDA = data, SCL = clock [OK]

Common Mistakes:

• Confusing I2C lines with SPI lines
• Mixing data and clock line names
• Assuming more than two lines are used

2. Which of the following correctly describes the state of the SDA and SCL lines when no device is pulling them low on an I2C bus?

easy

A. SDA is high, SCL is low

B. Both lines are low

C. SDA is low, SCL is high

D. Both lines are high

Solution

1. Step 1: Understand line behavior on I2C bus

   Lines are open-drain and pulled high by resistors when released.

2. Step 2: Determine line state when idle

   When no device pulls lines low, both SDA and SCL remain high.

3. Final Answer:

   Both lines are high -> Option D

4. Quick Check:

   Idle I2C lines = high [OK]

Hint: Lines float high unless pulled low [OK]

Common Mistakes:

• Assuming lines default to low
• Confusing line states during communication
• Ignoring pull-up resistor effect

3. Consider this snippet controlling I2C lines in embedded C:

if (SDA == 1 && SCL == 1) {
    // Start condition detected
} else if (SDA == 0 && SCL == 1) {
    // Stop condition detected
}

What is the output behavior of this code snippet?

medium

A. Detects start when SDA goes low while SCL is high

B. Detects stop when SDA goes high while SCL is low

C. Detects start when SDA and SCL are both low

D. Detects stop when SDA and SCL are both high

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls low while SCL is high. Stop condition: SDA rises high while SCL is high.

2. Step 2: Analyze code conditions

   The code checks if SDA and SCL are both high for start, which is incorrect; start is when SDA falls low while SCL is high.

3. Final Answer:

   Detects start when SDA goes low while SCL is high -> Option A

4. Quick Check:

   Start = SDA low + SCL high [OK]

Hint: Start = SDA falls low while SCL high [OK]

Common Mistakes:

• Mixing start and stop conditions
• Checking both lines high for start
• Ignoring SDA line change direction

4. This embedded C code snippet is intended to detect an I2C stop condition:

if (SDA == 1 && SCL == 0) {
    // Stop condition detected
}

What is the error in this code?

medium

A. Stop condition requires SCL to be high, not low

B. SDA should be low, not high for stop condition

C. Both SDA and SCL should be low for stop condition

D. No error; code correctly detects stop condition

Solution

1. Step 1: Recall stop condition timing

   Stop condition occurs when SDA rises from low to high while SCL is high.

2. Step 2: Check code condition

   The code checks SDA high and SCL low, which is incorrect; SCL must be high for stop.

3. Final Answer:

   Stop condition requires SCL to be high, not low -> Option A

4. Quick Check:

   Stop = SDA high + SCL high [OK]

Hint: Stop needs SCL high, not low [OK]

Common Mistakes:

• Confusing clock line state for stop
• Assuming SDA low means stop
• Ignoring line state transitions

5. You want to implement a function in embedded C that waits for the I2C start condition before proceeding. Which logic correctly detects the start condition on SDA and SCL lines?

hard

A. Wait until SDA changes from low to high while SCL is low

B. Wait until SDA changes from high to low while SCL is high

C. Wait until both SDA and SCL are low simultaneously

D. Wait until SCL changes from low to high while SDA is low

Solution

1. Step 1: Understand start condition in I2C

   Start condition is when SDA line falls from high to low while SCL line is high.

2. Step 2: Match logic to condition

   Wait until SDA changes from high to low while SCL is high correctly waits for SDA falling edge with SCL high, matching start condition.

3. Final Answer:

   Wait until SDA changes from high to low while SCL is high -> Option B

4. Quick Check:

   Start = SDA high-to-low + SCL high [OK]

Hint: Start = SDA falls low while SCL high [OK]

Common Mistakes:

• Waiting for SDA rising edge instead of falling
• Checking SCL low instead of high
• Confusing start with stop condition