I2C bus architecture (SDA, SCL) in Embedded C - Step-by-Step Execution

Concept Flow - I2C bus architecture (SDA, SCL)

Start Condition

↓

Master sends clock on SCL

↓

Master sends data bit on SDA

↓

Slave reads data bit on SDA

↓

Master waits for ACK from Slave

↓

Repeat for all bits

↓

Stop Condition

The I2C bus uses two lines: SDA for data and SCL for clock. The master controls the clock and data bits, and the slave responds with acknowledgments.

Execution Sample

Embedded C

void i2c_write_bit(int bit) {
  set_SDA(bit);       // Set data line
  set_SCL(1);        // Clock high
  delay();           // Wait
  set_SCL(0);        // Clock low
}

This code sends one bit on the I2C bus by setting SDA and toggling SCL.

Execution Table

Step	SCL (Clock)	SDA (Data)	Action	Result
1	0	Start (High)	Start Condition: SDA goes low while SCL is high	Bus ready for data
2	0->1	1	Set SDA to 1, then SCL high	Data bit 1 sent
3	1->0	1	SCL goes low	Prepare for next bit
4	0->1	0	Set SDA to 0, then SCL high	Data bit 0 sent
5	1->0	0	SCL goes low	Prepare for next bit
6	0->1	ACK (Slave pulls SDA low)	Slave acknowledges	Master receives ACK
7	1->0	ACK	SCL goes low	Ready for next byte or stop
8	1	Stop (Low->High)	Stop Condition: SDA goes high while SCL is high	Bus released

💡 Stop condition ends communication, SDA and SCL return to idle high state

Variable Tracker

Signal Line	Start	After Step 2	After Step 4	After Step 6	After Step 8
SCL	1 (idle)	1	1	1	1 (idle)
SDA	1 (idle)	1	0	0 (ACK low)	1 (idle)

Key Moments - 2 Insights

Why does SDA change only when SCL is low except for start and stop?

Because data bits on SDA must be stable when SCL is high to be read correctly. This is shown in steps 2 and 4 where SDA changes before SCL goes high.

What is the purpose of the ACK bit from the slave?

The ACK bit (step 6) lets the master know the slave received the data. The slave pulls SDA low during SCL high to acknowledge.

Visual Quiz - 3 Questions

Look at the execution table, what is the state of SDA during step 4?

A High (1)

B Low (0)

C Floating

D Toggling

💡 Hint

Check the SDA column in row for step 4 in the execution_table

At which step does the slave send an acknowledgment?

A Step 2

B Step 4

C Step 6

D Step 8

💡 Hint

Look for the ACK action in the execution_table rows

If SDA changed while SCL was high during data bits, what would happen?

A Data would be read incorrectly

B Communication would speed up

C Slave would send NACK

D Nothing changes

💡 Hint

Refer to key_moments about SDA stability during SCL high

Concept Snapshot

I2C uses two lines: SDA (data) and SCL (clock).
Master controls SCL and sets SDA bits.
Data bits must be stable when SCL is high.
Start: SDA falls while SCL high.
Stop: SDA rises while SCL high.
Slave ACKs by pulling SDA low during SCL high.

Full Transcript

The I2C bus architecture uses two wires: SDA for data and SCL for clock. Communication starts with a start condition where SDA goes low while SCL is high. The master sends data bits by setting SDA and toggling SCL. Data bits must be stable when SCL is high so the slave can read them correctly. After each byte, the slave sends an acknowledgment by pulling SDA low during the clock pulse. Communication ends with a stop condition where SDA goes high while SCL is high. This ensures clear signaling and synchronization between master and slave devices on the bus.