I2C bus architecture (SDA, SCL) in Embedded C - Cheat Sheet & Quick Revision

Recall & Review

beginner

What does SDA stand for in I2C bus architecture?

SDA stands for Serial Data Line. It is the line used for transferring data between devices on the I2C bus.

beginner

What is the role of the SCL line in I2C communication?

SCL stands for Serial Clock Line. It provides the clock signal that synchronizes data transfer on the I2C bus.

intermediate

Why are SDA and SCL lines open-drain/open-collector in I2C?

They are open-drain/open-collector to allow multiple devices to share the bus without conflicts. Devices can only pull the line low, and a pull-up resistor brings the line high when no device is pulling it low.

intermediate

How does the master device use SDA and SCL to start communication on the I2C bus?

The master generates a START condition by pulling SDA low while SCL is high. This signals all devices that a communication session is beginning.

intermediate

What happens on the I2C bus when the master sends a STOP condition?

The master releases SDA from low to high while SCL is high. This signals the end of communication and frees the bus for other devices.

What does the SDA line do in I2C communication?

A Transfers data between devices

B Provides the clock signal

C Supplies power to devices

D Resets the bus

SDA is the Serial Data Line used to transfer data between devices on the I2C bus.

Why are pull-up resistors used on SDA and SCL lines?

A To allow devices to pull lines low safely

B To provide power to the devices

C To speed up data transfer

D To prevent devices from communicating

Pull-up resistors ensure the lines go high when no device pulls them low, enabling safe open-drain communication.

What condition does the master generate to start communication on the I2C bus?

A STOP condition

B START condition

C RESET condition

D ACK condition

The START condition is generated by pulling SDA low while SCL is high to begin communication.

Which line carries the clock signal in I2C?

A SDA

B SCL

C VCC

D GND

SCL is the Serial Clock Line that provides the clock signal for synchronization.

What does an open-drain configuration allow on the I2C bus?

A Multiple devices to drive the line high simultaneously

B Multiple devices to safely pull the line low without conflict

C Only one device to communicate at a time

D Faster data transfer speeds

Open-drain allows multiple devices to pull the line low safely, avoiding conflicts on the bus.

Explain the roles of SDA and SCL lines in the I2C bus architecture.

Think about how devices talk and keep time on the bus.

Describe how the I2C master starts and stops communication using SDA and SCL lines.

Focus on the changes in SDA line while SCL is high.

Practice

1. Which two lines are used in the I2C bus architecture for communication?

easy

A. CLK for data and DAT for clock

B. TX for data and RX for clock

C. SDA for data and SCL for clock

D. MOSI for data and MISO for clock

Solution

1. Step 1: Recall I2C bus lines

   I2C uses two specific lines: SDA and SCL.

2. Step 2: Identify roles of lines

   SDA carries data, and SCL carries the clock signal.

3. Final Answer:

   SDA for data and SCL for clock -> Option C

4. Quick Check:

   I2C lines = SDA + SCL [OK]

Hint: Remember: SDA = data, SCL = clock [OK]

Common Mistakes:

• Confusing I2C lines with SPI lines
• Mixing data and clock line names
• Assuming more than two lines are used

2. Which of the following correctly describes the state of the SDA and SCL lines when no device is pulling them low on an I2C bus?

easy

A. SDA is high, SCL is low

B. Both lines are low

C. SDA is low, SCL is high

D. Both lines are high

Solution

1. Step 1: Understand line behavior on I2C bus

   Lines are open-drain and pulled high by resistors when released.

2. Step 2: Determine line state when idle

   When no device pulls lines low, both SDA and SCL remain high.

3. Final Answer:

   Both lines are high -> Option D

4. Quick Check:

   Idle I2C lines = high [OK]

Hint: Lines float high unless pulled low [OK]

Common Mistakes:

• Assuming lines default to low
• Confusing line states during communication
• Ignoring pull-up resistor effect

3. Consider this snippet controlling I2C lines in embedded C:

if (SDA == 1 && SCL == 1) {
    // Start condition detected
} else if (SDA == 0 && SCL == 1) {
    // Stop condition detected
}

What is the output behavior of this code snippet?

medium

A. Detects start when SDA goes low while SCL is high

B. Detects stop when SDA goes high while SCL is low

C. Detects start when SDA and SCL are both low

D. Detects stop when SDA and SCL are both high

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls low while SCL is high. Stop condition: SDA rises high while SCL is high.

2. Step 2: Analyze code conditions

   The code checks if SDA and SCL are both high for start, which is incorrect; start is when SDA falls low while SCL is high.

3. Final Answer:

   Detects start when SDA goes low while SCL is high -> Option A

4. Quick Check:

   Start = SDA low + SCL high [OK]

Hint: Start = SDA falls low while SCL high [OK]

Common Mistakes:

• Mixing start and stop conditions
• Checking both lines high for start
• Ignoring SDA line change direction

4. This embedded C code snippet is intended to detect an I2C stop condition:

if (SDA == 1 && SCL == 0) {
    // Stop condition detected
}

What is the error in this code?

medium

A. Stop condition requires SCL to be high, not low

B. SDA should be low, not high for stop condition

C. Both SDA and SCL should be low for stop condition

D. No error; code correctly detects stop condition

Solution

1. Step 1: Recall stop condition timing

   Stop condition occurs when SDA rises from low to high while SCL is high.

2. Step 2: Check code condition

   The code checks SDA high and SCL low, which is incorrect; SCL must be high for stop.

3. Final Answer:

   Stop condition requires SCL to be high, not low -> Option A

4. Quick Check:

   Stop = SDA high + SCL high [OK]

Hint: Stop needs SCL high, not low [OK]

Common Mistakes:

• Confusing clock line state for stop
• Assuming SDA low means stop
• Ignoring line state transitions

5. You want to implement a function in embedded C that waits for the I2C start condition before proceeding. Which logic correctly detects the start condition on SDA and SCL lines?

hard

A. Wait until SDA changes from low to high while SCL is low

B. Wait until SDA changes from high to low while SCL is high

C. Wait until both SDA and SCL are low simultaneously

D. Wait until SCL changes from low to high while SDA is low

Solution

1. Step 1: Understand start condition in I2C

   Start condition is when SDA line falls from high to low while SCL line is high.

2. Step 2: Match logic to condition

   Wait until SDA changes from high to low while SCL is high correctly waits for SDA falling edge with SCL high, matching start condition.

3. Final Answer:

   Wait until SDA changes from high to low while SCL is high -> Option B

4. Quick Check:

   Start = SDA high-to-low + SCL high [OK]

Hint: Start = SDA falls low while SCL high [OK]

Common Mistakes:

• Waiting for SDA rising edge instead of falling
• Checking SCL low instead of high
• Confusing start with stop condition