I2C bus architecture (SDA, SCL) in Embedded C - Time & Space Complexity

Time Complexity: I2C bus architecture (SDA, SCL)

O(n)

Understanding Time Complexity

We want to understand how the time to communicate on an I2C bus changes as we send more data.

How does the number of bits sent affect the total time taken?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

// Send one byte over I2C
void i2c_send_byte(uint8_t data) {
    for (int i = 0; i < 8; i++) {
        // Set SDA line to bit value
        SDA = (data & 0x80) ? 1 : 0;
        data <<= 1;
        // Toggle SCL line to clock the bit
        SCL = 1;
        delay();
        SCL = 0;
        delay();
    }
}
    

This code sends one byte (8 bits) over the I2C bus by setting the data line (SDA) and toggling the clock line (SCL) for each bit.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The for-loop that sends each bit of the byte.
• How many times: Exactly 8 times, once for each bit in the byte.

How Execution Grows With Input

Each byte sent requires 8 clock cycles. If we send more bytes, the time grows by 8 times the number of bytes.

Input Size (bytes)	Approx. Operations (bit clocks)
10	80
100	800
1000	8000

Pattern observation: The time grows linearly with the number of bytes sent.

Final Time Complexity

Time Complexity: O(n)

This means the time to send data grows directly in proportion to the number of bytes you send.

Common Mistake

[X] Wrong: "Sending more bytes takes the same time as sending one byte because the clock speed is fixed."

[OK] Correct: Even though the clock speed is fixed, each byte requires multiple clock cycles, so more bytes mean more total time.

Interview Connect

Understanding how communication time grows with data size helps you design efficient embedded systems and explain your reasoning clearly in interviews.

Self-Check

"What if we changed the code to send 16 bits instead of 8 bits per data unit? How would the time complexity change?"

Practice

1. Which two lines are used in the I2C bus architecture for communication?

easy

A. CLK for data and DAT for clock

B. TX for data and RX for clock

C. SDA for data and SCL for clock

D. MOSI for data and MISO for clock

Solution

1. Step 1: Recall I2C bus lines

   I2C uses two specific lines: SDA and SCL.

2. Step 2: Identify roles of lines

   SDA carries data, and SCL carries the clock signal.

3. Final Answer:

   SDA for data and SCL for clock -> Option C

4. Quick Check:

   I2C lines = SDA + SCL [OK]

Hint: Remember: SDA = data, SCL = clock [OK]

Common Mistakes:

• Confusing I2C lines with SPI lines
• Mixing data and clock line names
• Assuming more than two lines are used

2. Which of the following correctly describes the state of the SDA and SCL lines when no device is pulling them low on an I2C bus?

easy

A. SDA is high, SCL is low

B. Both lines are low

C. SDA is low, SCL is high

D. Both lines are high

Solution

1. Step 1: Understand line behavior on I2C bus

   Lines are open-drain and pulled high by resistors when released.

2. Step 2: Determine line state when idle

   When no device pulls lines low, both SDA and SCL remain high.

3. Final Answer:

   Both lines are high -> Option D

4. Quick Check:

   Idle I2C lines = high [OK]

Hint: Lines float high unless pulled low [OK]

Common Mistakes:

• Assuming lines default to low
• Confusing line states during communication
• Ignoring pull-up resistor effect

3. Consider this snippet controlling I2C lines in embedded C:

if (SDA == 1 && SCL == 1) {
    // Start condition detected
} else if (SDA == 0 && SCL == 1) {
    // Stop condition detected
}

What is the output behavior of this code snippet?

medium

A. Detects start when SDA goes low while SCL is high

B. Detects stop when SDA goes high while SCL is low

C. Detects start when SDA and SCL are both low

D. Detects stop when SDA and SCL are both high

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls low while SCL is high. Stop condition: SDA rises high while SCL is high.

2. Step 2: Analyze code conditions

   The code checks if SDA and SCL are both high for start, which is incorrect; start is when SDA falls low while SCL is high.

3. Final Answer:

   Detects start when SDA goes low while SCL is high -> Option A

4. Quick Check:

   Start = SDA low + SCL high [OK]

Hint: Start = SDA falls low while SCL high [OK]

Common Mistakes:

• Mixing start and stop conditions
• Checking both lines high for start
• Ignoring SDA line change direction

4. This embedded C code snippet is intended to detect an I2C stop condition:

if (SDA == 1 && SCL == 0) {
    // Stop condition detected
}

What is the error in this code?

medium

A. Stop condition requires SCL to be high, not low

B. SDA should be low, not high for stop condition

C. Both SDA and SCL should be low for stop condition

D. No error; code correctly detects stop condition

Solution

1. Step 1: Recall stop condition timing

   Stop condition occurs when SDA rises from low to high while SCL is high.

2. Step 2: Check code condition

   The code checks SDA high and SCL low, which is incorrect; SCL must be high for stop.

3. Final Answer:

   Stop condition requires SCL to be high, not low -> Option A

4. Quick Check:

   Stop = SDA high + SCL high [OK]

Hint: Stop needs SCL high, not low [OK]

Common Mistakes:

• Confusing clock line state for stop
• Assuming SDA low means stop
• Ignoring line state transitions

5. You want to implement a function in embedded C that waits for the I2C start condition before proceeding. Which logic correctly detects the start condition on SDA and SCL lines?

hard

A. Wait until SDA changes from low to high while SCL is low

B. Wait until SDA changes from high to low while SCL is high

C. Wait until both SDA and SCL are low simultaneously

D. Wait until SCL changes from low to high while SDA is low

Solution

1. Step 1: Understand start condition in I2C

   Start condition is when SDA line falls from high to low while SCL line is high.

2. Step 2: Match logic to condition

   Wait until SDA changes from high to low while SCL is high correctly waits for SDA falling edge with SCL high, matching start condition.

3. Final Answer:

   Wait until SDA changes from high to low while SCL is high -> Option B

4. Quick Check:

   Start = SDA high-to-low + SCL high [OK]

Hint: Start = SDA falls low while SCL high [OK]

Common Mistakes:

• Waiting for SDA rising edge instead of falling
• Checking SCL low instead of high
• Confusing start with stop condition