I2C bus architecture (SDA, SCL) in Embedded C - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

I2C SDA Line Behavior in Open-Drain Configuration

Consider the following embedded C code snippet simulating the behavior of the SDA line in an I2C bus with open-drain configuration. What will be the final state of the SDA line after executing this code?

Embedded C

/* SDA line simulated as a variable: 0 = low, 1 = released (pulled high by resistor) */
int SDA = 1; // Initially released (high)

// Device A pulls SDA low
SDA = 0;

// Device B tries to release SDA
SDA = 1;

// What is the actual SDA line state now?
int final_SDA = SDA;

A final_SDA = 0; // SDA remains low because open-drain lines are wired-AND

B final_SDA = -1; // Error state, line conflict

C final_SDA = 1; // SDA goes high because Device B released it

D final_SDA = 2; // Undefined state

💡 Hint

Remember that in I2C, devices can only pull the line low or release it. The line state is the logical AND of all devices' outputs.

In an open-drain configuration, the SDA line is pulled low if any device pulls it low. Even if Device B releases the line, Device A pulling it low keeps the line low.

❓ Predict Output

intermediate

I2C Clock Stretching Effect on SCL Line

Given the following code snippet simulating clock stretching on the I2C SCL line, what will be the output value of SCL after Device B stretches the clock?

Embedded C

/* SCL line simulated as a variable: 0 = low, 1 = released (pulled high by resistor) */
int SCL = 1; // Initially released (high)

// Device A tries to release SCL
SCL = 1;

// Device B pulls SCL low to stretch clock
SCL = 0;

// What is the actual SCL line state now?
int final_SCL = SCL;

A final_SCL = 2; // Undefined state

B final_SCL = 1; // SCL is high because Device A released it

C final_SCL = -1; // Bus error due to conflict

D final_SCL = 0; // SCL is low due to clock stretching by Device B

💡 Hint

Clock stretching means a device holds the clock line low to delay communication.

When Device B pulls SCL low, the line stays low regardless of Device A releasing it, effectively stretching the clock.

🔧 Debug

advanced

Identify the Bug in I2C SDA Line Handling Code

The following embedded C code attempts to simulate the SDA line behavior in an I2C bus. However, it does not correctly represent the open-drain logic. What is the bug causing incorrect SDA line state?

Embedded C

int SDA = 1; // Released (high)

void deviceA_pull_low() {
    SDA = 0; // Device A pulls SDA low
}

void deviceB_release() {
    SDA = 1; // Device B releases SDA
}

void main() {
    deviceA_pull_low();
    deviceB_release();
    // Expected SDA to be low, but SDA is 1
}

A Missing delay after deviceB_release() causing race condition

B SDA variable is overwritten by last device instead of combining outputs with wired-AND logic

C Device B should pull SDA low instead of releasing it

D SDA line should be initialized to 0 instead of 1

💡 Hint

Think about how multiple devices affect the line state simultaneously in open-drain wiring.

The code overwrites SDA directly, losing the combined effect of multiple devices. The SDA line state should be the logical AND of all devices' outputs, not just the last assignment.

📝 Syntax

advanced

Syntax Error in I2C SCL Line Control Code

Which option contains the correct syntax to set the SCL line low in embedded C, assuming SCL is a GPIO pin controlled by a macro GPIO_WritePin(port, pin, value)?

Embedded C

/* Assume port and pin are defined as I2C_PORT and I2C_SCL_PIN respectively */

A GPIO_WritePin(I2C_PORT, I2C_SCL_PIN, LOW);

B GPIO_WritePin(I2C_PORT, I2C_SCL_PIN == 0);

C GPIO_WritePin(I2C_PORT, I2C_SCL_PIN, 0);

D GPIO_WritePin(I2C_PORT, I2C_SCL_PIN 0);

💡 Hint

Check the function call syntax and parameters.

Option C correctly calls the function with three parameters: port, pin, and value 0 to set low. Option C uses comparison instead of parameter. Option C uses undefined LOW. Option C misses a comma.

🚀 Application

expert

Calculate Number of Devices on I2C Bus from SDA and SCL States

You have an I2C bus with multiple devices connected. The SDA and SCL lines are open-drain and pulled high by resistors. You observe the following states during a bus scan:

• SDA line is low
• SCL line is high

Assuming each device can pull SDA low independently, and the bus line state is the logical AND of all devices' outputs, what is the minimum number of devices pulling SDA low?

A At least 1 device is pulling SDA low

B At least 2 devices are pulling SDA low

C No devices are pulling SDA low

D All devices are releasing SDA

💡 Hint

If the SDA line is low, what does that tell you about devices connected?

Since the SDA line is low, at least one device must be pulling it low. The line is low if any device pulls it low due to open-drain wiring.

Practice

1. Which two lines are used in the I2C bus architecture for communication?

easy

A. CLK for data and DAT for clock

B. TX for data and RX for clock

C. SDA for data and SCL for clock

D. MOSI for data and MISO for clock

Solution

1. Step 1: Recall I2C bus lines

   I2C uses two specific lines: SDA and SCL.

2. Step 2: Identify roles of lines

   SDA carries data, and SCL carries the clock signal.

3. Final Answer:

   SDA for data and SCL for clock -> Option C

4. Quick Check:

   I2C lines = SDA + SCL [OK]

Hint: Remember: SDA = data, SCL = clock [OK]

Common Mistakes:

• Confusing I2C lines with SPI lines
• Mixing data and clock line names
• Assuming more than two lines are used

2. Which of the following correctly describes the state of the SDA and SCL lines when no device is pulling them low on an I2C bus?

easy

A. SDA is high, SCL is low

B. Both lines are low

C. SDA is low, SCL is high

D. Both lines are high

Solution

1. Step 1: Understand line behavior on I2C bus

   Lines are open-drain and pulled high by resistors when released.

2. Step 2: Determine line state when idle

   When no device pulls lines low, both SDA and SCL remain high.

3. Final Answer:

   Both lines are high -> Option D

4. Quick Check:

   Idle I2C lines = high [OK]

Hint: Lines float high unless pulled low [OK]

Common Mistakes:

• Assuming lines default to low
• Confusing line states during communication
• Ignoring pull-up resistor effect

3. Consider this snippet controlling I2C lines in embedded C:

if (SDA == 1 && SCL == 1) {
    // Start condition detected
} else if (SDA == 0 && SCL == 1) {
    // Stop condition detected
}

What is the output behavior of this code snippet?

medium

A. Detects start when SDA goes low while SCL is high

B. Detects stop when SDA goes high while SCL is low

C. Detects start when SDA and SCL are both low

D. Detects stop when SDA and SCL are both high

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls low while SCL is high. Stop condition: SDA rises high while SCL is high.

2. Step 2: Analyze code conditions

   The code checks if SDA and SCL are both high for start, which is incorrect; start is when SDA falls low while SCL is high.

3. Final Answer:

   Detects start when SDA goes low while SCL is high -> Option A

4. Quick Check:

   Start = SDA low + SCL high [OK]

Hint: Start = SDA falls low while SCL high [OK]

Common Mistakes:

• Mixing start and stop conditions
• Checking both lines high for start
• Ignoring SDA line change direction

4. This embedded C code snippet is intended to detect an I2C stop condition:

if (SDA == 1 && SCL == 0) {
    // Stop condition detected
}

What is the error in this code?

medium

A. Stop condition requires SCL to be high, not low

B. SDA should be low, not high for stop condition

C. Both SDA and SCL should be low for stop condition

D. No error; code correctly detects stop condition

Solution

1. Step 1: Recall stop condition timing

   Stop condition occurs when SDA rises from low to high while SCL is high.

2. Step 2: Check code condition

   The code checks SDA high and SCL low, which is incorrect; SCL must be high for stop.

3. Final Answer:

   Stop condition requires SCL to be high, not low -> Option A

4. Quick Check:

   Stop = SDA high + SCL high [OK]

Hint: Stop needs SCL high, not low [OK]

Common Mistakes:

• Confusing clock line state for stop
• Assuming SDA low means stop
• Ignoring line state transitions

5. You want to implement a function in embedded C that waits for the I2C start condition before proceeding. Which logic correctly detects the start condition on SDA and SCL lines?

hard

A. Wait until SDA changes from low to high while SCL is low

B. Wait until SDA changes from high to low while SCL is high

C. Wait until both SDA and SCL are low simultaneously

D. Wait until SCL changes from low to high while SDA is low

Solution

1. Step 1: Understand start condition in I2C

   Start condition is when SDA line falls from high to low while SCL line is high.

2. Step 2: Match logic to condition

   Wait until SDA changes from high to low while SCL is high correctly waits for SDA falling edge with SCL high, matching start condition.

3. Final Answer:

   Wait until SDA changes from high to low while SCL is high -> Option B

4. Quick Check:

   Start = SDA high-to-low + SCL high [OK]

Hint: Start = SDA falls low while SCL high [OK]

Common Mistakes:

• Waiting for SDA rising edge instead of falling
• Checking SCL low instead of high
• Confusing start with stop condition