Condition flags (N, Z, C, V) in ARM Architecture

Introduction

Condition flags help the processor know the result of an operation. They tell if a number is negative, zero, if there was a carry out, or if an overflow happened.

To decide if a number is positive, negative, or zero after a calculation.

To check if an addition or subtraction caused a carry or borrow.

To detect if an arithmetic operation caused an overflow beyond the allowed number size.

To control program flow by making decisions based on previous results.

To optimize code by skipping unnecessary instructions depending on conditions.

Core Concept

ARM Architecture

N - Negative flag
Z - Zero flag
C - Carry flag
V - Overflow flag

N (Negative flag): Set if the result is negative (usually if the highest bit is 1).

Z (Zero flag): Set if the result is zero.

C (Carry flag): Set if an addition produces a carry out or subtraction requires a borrow.

V (Overflow flag): Set if signed arithmetic overflow occurs.

Key Points

Shows flags after adding a positive and a negative number resulting in a negative value.

ARM Architecture

After adding 5 + (-10):
N = 1 (result negative)
Z = 0 (result not zero)
C = 0 (no carry)
V = 0 (no overflow)

Flags indicate the result is zero and no borrow occurred.

ARM Architecture

After subtracting 3 - 3:
N = 0
Z = 1 (result is zero)
C = 1 (no borrow needed)
V = 0

Carry flag set because the result exceeds 8-bit limit.

ARM Architecture

After adding 255 + 1 (8-bit):
N = 0
Z = 0
C = 1 (carry out)
V = 0

Overflow flag set because signed addition exceeded positive range.

ARM Architecture

After adding 127 + 1 (signed 8-bit):
N = 1
Z = 0
C = 0
V = 1 (overflow)

Detailed Explanation

This example adds 127 and 1 using the ADDS instruction, which updates the condition flags. The result is 128, which sets the Negative (N) and Overflow (V) flags because 128 is negative in signed 8-bit and the addition overflowed the signed range.

ARM Architecture

MOV R0, #127       ; Load 127 into R0
MOV R1, #1         ; Load 1 into R1
ADDS R2, R0, R1    ; Add R0 and R1, update flags

; Check flags
; N = Negative flag
; Z = Zero flag
; C = Carry flag
; V = Overflow flag

; In ARM, after ADDS, flags are set based on result

; Here, R2 = 128 (0x80), which is negative in signed 8-bit
; Overflow occurs because 127 + 1 exceeds signed max

; We can read flags in CPSR register (not shown here)

Important Notes

Flags are updated automatically by certain instructions that end with 'S' like ADDS or SUBS.

Carry flag is important for multi-word arithmetic where numbers are larger than the processor word size.

Overflow flag only applies to signed arithmetic, not unsigned.

Summary

Condition flags (N, Z, C, V) tell the processor about the result of operations.

N means negative result, Z means zero result, C means carry out or borrow, V means signed overflow.

These flags help control program decisions and handle arithmetic correctly.

Practice

1. Which condition flag in ARM architecture indicates that the result of an operation is zero?

easy

A. Z flag

B. N flag

C. C flag

D. V flag

Solution

1. Step 1: Understand the meaning of each flag

   The Z flag is set when the result of an operation is zero. The N flag indicates a negative result, C is for carry or borrow, and V is for signed overflow.

2. Step 2: Identify the zero result flag

   Since the question asks for the flag indicating zero result, the correct flag is Z.

3. Final Answer:

   Z flag -> Option A

4. Quick Check:

   Zero result = Z flag [OK]

Hint: Zero result always sets the Z flag [OK]

Common Mistakes:

• Confusing N (negative) with Z (zero)
• Thinking C means zero result
• Mixing V (overflow) with zero flag

2. Which of the following is the correct way to check the Negative flag (N) in ARM assembly condition codes?

easy

A. BMI (Branch if Minus)

B. BEQ (Branch if Equal)

C. BHS (Branch if Higher or Same)

D. BVS (Branch if Overflow Set)

Solution

1. Step 1: Recall ARM condition codes

   BEQ checks Z flag (zero), BMI checks N flag (negative), BHS checks C flag (carry set), and BVS checks V flag (overflow).

2. Step 2: Match the condition code to N flag

   The correct code for checking the Negative flag is BMI (Branch if Minus).

3. Final Answer:

   BMI (Branch if Minus) -> Option A

4. Quick Check:

   Negative flag = BMI [OK]

Hint: BMI always checks the Negative (N) flag [OK]

Common Mistakes:

• Using BEQ for negative instead of zero
• Confusing BHS with N flag
• Mixing BVS (overflow) with negative flag

3. Consider an ARM instruction that adds two 8-bit numbers: 0x7F + 0x01. Which condition flags will be set after this operation?

medium

A. N=0, Z=1, C=0, V=0

B. N=0, Z=0, C=1, V=0

C. N=1, Z=0, C=1, V=1

D. N=1, Z=0, C=0, V=1

Solution

1. Step 1: Calculate the sum and check overflow

   0x7F (127 decimal) + 0x01 (1 decimal) = 128 decimal (0x80). This fits in 8 bits but crosses the positive max for signed 8-bit (127), causing signed overflow.

2. Step 2: Determine flags

   N flag is 1 (MSB of 0x80 is 1, negative result), Z=0 since result is not zero, C=0 because no carry out beyond 8 bits, V=1 because signed overflow occurred.

3. Final Answer:

   N=1, Z=0, C=0, V=1 -> Option D

4. Quick Check:

   Signed overflow sets V=1, no zero or carry [OK]

Hint: Overflow sets V, zero result sets Z, carry sets C [OK]

Common Mistakes:

• Confusing carry with overflow
• Assuming zero flag set for non-zero result
• Misinterpreting negative flag for unsigned sum

4. An ARM instruction adds 0xFF and 0x02 and sets the condition flags. The flags are incorrectly showing C=0. What is the likely error?

medium

A. The addition result was zero, so C should be 0

B. The instruction did not update the condition flags

C. The V flag was set instead of C flag

D. The processor does not support carry flag

Solution

1. Step 1: Analyze the addition and expected flags

   0xFF (255) + 0x02 (2) = 0x101 (257), which exceeds 8 bits, so carry (C) should be set to 1.

2. Step 2: Identify why C flag is 0

   If C=0 incorrectly, likely the instruction did not update the condition flags because the 'S' suffix (e.g., ADDS) was missing, so flags were not changed.

3. Final Answer:

   The instruction did not update the condition flags -> Option B

4. Quick Check:

   Missing 'S' means flags unchanged [OK]

Hint: Use 'S' suffix to update flags after arithmetic [OK]

Common Mistakes:

• Assuming carry flag updates automatically
• Confusing overflow (V) with carry (C)
• Believing processor lacks carry flag

5. You want to write an ARM assembly routine that subtracts two numbers and branches if the result is negative or zero. Which condition flags and branch instructions should you use together?

hard

A. Check V flag with BVC and C flag with BCC, branch if both clear

B. Check C flag with BCS and V flag with BVS, branch if either set

C. Check N flag with BMI and Z flag with BEQ, branch if either set

D. Check Z flag with BNE and N flag with BPL, branch if both clear

Solution

1. Step 1: Identify flags for negative and zero results

   Negative result sets N flag, zero result sets Z flag.

2. Step 2: Choose branch instructions for these flags

   BMI branches if N=1 (negative), BEQ branches if Z=1 (zero). To branch if either negative or zero, use BMI and BEQ together.

3. Final Answer:

   Check N flag with BMI and Z flag with BEQ, branch if either set -> Option C

4. Quick Check:

   Negative = BMI, Zero = BEQ [OK]

Hint: Use BMI for negative and BEQ for zero branches [OK]

Common Mistakes:

• Using BNE instead of BEQ for zero
• Confusing carry or overflow flags for sign checks
• Trying to branch on both flags cleared instead of set