Condition flags (N, Z, C, V) in ARM Architecture - Step-by-Step Execution

Concept Flow - Condition flags (N, Z, C, V)

Instruction Executes

↓

Result Computed

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Check Result Bits

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Set Flags N, Z, C, V

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Use Flags for Conditional Execution

After an instruction runs, the CPU checks the result and sets four flags (N, Z, C, V) that tell about the result's sign, zero, carry, and overflow. These flags help decide what to do next.

Execution Sample

ARM Architecture

MVNS R0, #0x7FFFFFFF
ADDS R0, R0, #1
; Flags updated after ADDS

Add 1 to the largest positive 32-bit number to see how flags N, Z, C, V change.

Analysis Table

Step	Operation	R0 Value (Hex)	N (Negative)	Z (Zero)	C (Carry)	V (Overflow)
1	MVNS R0, #0x7FFFFFFF	0x80000000	1	0	1	0
2	ADDS R0, R0, #1	0x80000001	1	0	1	0
3	Flags set after ADDS	0x80000001	1	0	1	0

💡 Instruction finished; flags reflect result sign (N=1), not zero (Z=0), carry out (C=1), no overflow (V=0)

State Tracker

Variable	Start	After MVNS	After ADDS	Final
R0	undefined	0x80000000	0x80000001	0x80000001
N	undefined	1	1	1
Z	undefined	0	0	0
C	undefined	1	1	1
V	undefined	0	0	0

Key Insights - 3 Insights

Why is the Overflow flag (V) not set but the Carry flag (C) is after adding 1 to 0x80000000?

The Overflow flag (V) is not set because the signed addition did not overflow; the sign bit remained consistent. The Carry flag (C) is set because there was an unsigned carry out of the most significant bit. See execution_table step 2.

Why is the Negative flag (N) set after the addition?

The Negative flag (N) reflects the sign bit of the result. After addition, R0 is 0x80000001, which has the highest bit set, meaning the result is negative in signed terms. See variable_tracker for N changes.

Why is the Zero flag (Z) not set even though the result changed?

The Zero flag (Z) is only set if the result is exactly zero. Since 0x80000001 is not zero, Z remains cleared. See execution_table step 2.

Visual Quiz - 3 Questions

Look at the execution_table at step 2. What is the value of the Negative flag (N)?

A Undefined

B 0

C 1

D Cannot tell

💡 Hint

Check the 'N (Negative)' column in execution_table row for step 2.

At which step does the Carry flag (C) become set to 1?

A Step 2

B Step 1

C Step 3

D Never

💡 Hint

Look at the 'C (Carry)' column in execution_table rows.

If the ADD instruction added 0 instead of 1, how would the Zero flag (Z) change after step 2?

A Z would be 0

B Z would be undefined

C Z would be 1

D Z would toggle randomly

💡 Hint

Adding 0 keeps R0 at 0x80000000, which is not zero; check variable_tracker for Z behavior.

Concept Snapshot

Condition flags N, Z, C, V are set after arithmetic or logical instructions.
N = 1 if result is negative (sign bit set).
Z = 1 if result is zero.
C = 1 if carry out (unsigned overflow) occurs.
V = 1 if signed overflow occurs.
These flags guide conditional instructions in ARM CPUs.

Full Transcript

In ARM architecture, after an instruction runs, the CPU sets four condition flags: N (Negative), Z (Zero), C (Carry), and V (Overflow). These flags reflect the result's sign, whether it is zero, if an unsigned carry happened, or if a signed overflow occurred. For example, adding 1 to 0x7FFFFFFF results in 0x80000000, which sets N and V flags but not Z or C. These flags help the CPU decide what to do next, like branching or skipping instructions based on conditions.

Practice

1. Which condition flag in ARM architecture indicates that the result of an operation is zero?

easy

A. Z flag

B. N flag

C. C flag

D. V flag

Solution

1. Step 1: Understand the meaning of each flag

   The Z flag is set when the result of an operation is zero. The N flag indicates a negative result, C is for carry or borrow, and V is for signed overflow.

2. Step 2: Identify the zero result flag

   Since the question asks for the flag indicating zero result, the correct flag is Z.

3. Final Answer:

   Z flag -> Option A

4. Quick Check:

   Zero result = Z flag [OK]

Hint: Zero result always sets the Z flag [OK]

Common Mistakes:

• Confusing N (negative) with Z (zero)
• Thinking C means zero result
• Mixing V (overflow) with zero flag

2. Which of the following is the correct way to check the Negative flag (N) in ARM assembly condition codes?

easy

A. BMI (Branch if Minus)

B. BEQ (Branch if Equal)

C. BHS (Branch if Higher or Same)

D. BVS (Branch if Overflow Set)

Solution

1. Step 1: Recall ARM condition codes

   BEQ checks Z flag (zero), BMI checks N flag (negative), BHS checks C flag (carry set), and BVS checks V flag (overflow).

2. Step 2: Match the condition code to N flag

   The correct code for checking the Negative flag is BMI (Branch if Minus).

3. Final Answer:

   BMI (Branch if Minus) -> Option A

4. Quick Check:

   Negative flag = BMI [OK]

Hint: BMI always checks the Negative (N) flag [OK]

Common Mistakes:

• Using BEQ for negative instead of zero
• Confusing BHS with N flag
• Mixing BVS (overflow) with negative flag

3. Consider an ARM instruction that adds two 8-bit numbers: 0x7F + 0x01. Which condition flags will be set after this operation?

medium

A. N=0, Z=1, C=0, V=0

B. N=0, Z=0, C=1, V=0

C. N=1, Z=0, C=1, V=1

D. N=1, Z=0, C=0, V=1

Solution

1. Step 1: Calculate the sum and check overflow

   0x7F (127 decimal) + 0x01 (1 decimal) = 128 decimal (0x80). This fits in 8 bits but crosses the positive max for signed 8-bit (127), causing signed overflow.

2. Step 2: Determine flags

   N flag is 1 (MSB of 0x80 is 1, negative result), Z=0 since result is not zero, C=0 because no carry out beyond 8 bits, V=1 because signed overflow occurred.

3. Final Answer:

   N=1, Z=0, C=0, V=1 -> Option D

4. Quick Check:

   Signed overflow sets V=1, no zero or carry [OK]

Hint: Overflow sets V, zero result sets Z, carry sets C [OK]

Common Mistakes:

• Confusing carry with overflow
• Assuming zero flag set for non-zero result
• Misinterpreting negative flag for unsigned sum

4. An ARM instruction adds 0xFF and 0x02 and sets the condition flags. The flags are incorrectly showing C=0. What is the likely error?

medium

A. The addition result was zero, so C should be 0

B. The instruction did not update the condition flags

C. The V flag was set instead of C flag

D. The processor does not support carry flag

Solution

1. Step 1: Analyze the addition and expected flags

   0xFF (255) + 0x02 (2) = 0x101 (257), which exceeds 8 bits, so carry (C) should be set to 1.

2. Step 2: Identify why C flag is 0

   If C=0 incorrectly, likely the instruction did not update the condition flags because the 'S' suffix (e.g., ADDS) was missing, so flags were not changed.

3. Final Answer:

   The instruction did not update the condition flags -> Option B

4. Quick Check:

   Missing 'S' means flags unchanged [OK]

Hint: Use 'S' suffix to update flags after arithmetic [OK]

Common Mistakes:

• Assuming carry flag updates automatically
• Confusing overflow (V) with carry (C)
• Believing processor lacks carry flag

5. You want to write an ARM assembly routine that subtracts two numbers and branches if the result is negative or zero. Which condition flags and branch instructions should you use together?

hard

A. Check V flag with BVC and C flag with BCC, branch if both clear

B. Check C flag with BCS and V flag with BVS, branch if either set

C. Check N flag with BMI and Z flag with BEQ, branch if either set

D. Check Z flag with BNE and N flag with BPL, branch if both clear

Solution

1. Step 1: Identify flags for negative and zero results

   Negative result sets N flag, zero result sets Z flag.

2. Step 2: Choose branch instructions for these flags

   BMI branches if N=1 (negative), BEQ branches if Z=1 (zero). To branch if either negative or zero, use BMI and BEQ together.

3. Final Answer:

   Check N flag with BMI and Z flag with BEQ, branch if either set -> Option C

4. Quick Check:

   Negative = BMI, Zero = BEQ [OK]

Hint: Use BMI for negative and BEQ for zero branches [OK]

Common Mistakes:

• Using BNE instead of BEQ for zero
• Confusing carry or overflow flags for sign checks
• Trying to branch on both flags cleared instead of set