SCB (System Control Block) in ARM Architecture - Step-by-Step Execution

Concept Flow - SCB (System Control Block)

Start: CPU Reset

↓

SCB Initialization

↓

Configure System Control Registers

↓

Handle System Exceptions

↓

Manage Interrupts & Faults

↓

Provide System Status & Control

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CPU Executes Application Code

The SCB initializes after CPU reset, configures control registers, manages exceptions and interrupts, and provides system status before the CPU runs application code.

Execution Sample

ARM Architecture

SCB->AIRCR = 0x05FA0004;
if (SCB->ICSR & (1 << 27)) {
  // PendSV is pending
}
SCB->CCR |= (1 << 4);

This code writes to the Application Interrupt and Reset Control Register, checks if PendSV exception is pending, and sets a bit in the Configuration Control Register.

Analysis Table

Step	Register Accessed	Operation	Value Written/Read	Effect/Result
1	AIRCR	Write	0x05FA0004	Triggers system reset or priority grouping change
2	ICSR	Read	Bit 27 = 1	PendSV exception is pending
3	CCR	Read-Modify-Write	Set bit 4	Enables divide-by-zero trap
4	CPU	Execute	N/A	CPU continues with updated system control settings
5	N/A	Check	N/A	No further SCB register changes, normal operation

💡 All SCB registers configured and checked; CPU proceeds with normal execution.

State Tracker

Register	Initial	After Step 1	After Step 3	Final
AIRCR	Unknown	0x05FA0004	0x05FA0004	0x05FA0004
ICSR	Unknown	Bit 27=0 or 1	Bit 27=1	Bit 27=1
CCR	Unknown	Unknown	Bit 4 set	Bit 4 set

Key Insights - 3 Insights

Why do we write 0x05FA0004 to AIRCR instead of just 0x00000004?

The upper half-word 0x05FA is a key required to allow writes to AIRCR. Without it, the write is ignored. See execution_table step 1.

What does it mean when bit 27 of ICSR is set?

Bit 27 set indicates the PendSV exception is pending. This is shown in execution_table step 2.

Why do we set bit 4 in CCR?

Setting bit 4 in CCR enables trapping divide-by-zero errors, helping catch faults early. Refer to execution_table step 3.

Visual Quiz - 3 Questions

Look at the execution_table, what value is written to AIRCR at step 1?

A 0x05FA0000

B 0x00000004

C 0x05FA0004

D 0x00000000

💡 Hint

Check the 'Value Written/Read' column in execution_table row 1.

At which step does the system detect that PendSV is pending?

A Step 2

B Step 3

C Step 1

D Step 4

💡 Hint

Look at the 'Effect/Result' column for PendSV pending status in execution_table.

If bit 4 in CCR was not set at step 3, what would be the effect?

A PendSV exception would not be pending

B Divide-by-zero errors would not cause traps

C System reset would occur immediately

D AIRCR would reject writes

💡 Hint

Refer to key_moments about the purpose of setting bit 4 in CCR.

Concept Snapshot

SCB manages system control in ARM CPUs.
Key registers: AIRCR (reset control), ICSR (interrupt status), CCR (configuration).
AIRCR writes require a key (0x05FA) to allow changes.
ICSR bit 27 shows PendSV pending status.
CCR bit 4 enables divide-by-zero traps.
SCB helps handle exceptions and system control.

Full Transcript

The System Control Block (SCB) in ARM architecture is a set of registers that control system-level functions like resets, exceptions, and fault handling. After CPU reset, the SCB initializes and configures control registers such as AIRCR, ICSR, and CCR. Writing to AIRCR requires a special key (0x05FA) to allow changes. The ICSR register indicates pending exceptions like PendSV via bit 27. The CCR register controls system behavior, for example enabling divide-by-zero traps by setting bit 4. The SCB helps the CPU manage system exceptions and maintain control before running application code.

Practice

1. What is the primary role of the System Control Block (SCB) in ARM processors?

easy

A. Manage system-level control and handle exceptions

B. Store user application data

C. Control input/output peripherals

D. Manage memory allocation for programs

Solution

1. Step 1: Understand SCB's function in ARM

   The SCB is designed to manage system-level control tasks and handle exceptions such as faults and interrupts.

2. Step 2: Differentiate SCB from other components

   Unlike memory or peripheral controllers, SCB focuses on system control and exception handling.

3. Final Answer:

   Manage system-level control and handle exceptions -> Option A

4. Quick Check:

   SCB = system control and exceptions [OK]

Hint: SCB controls system and exceptions, not user data [OK]

Common Mistakes:

• Confusing SCB with peripheral controllers
• Thinking SCB manages user data
• Assuming SCB handles memory allocation

2. Which of the following is the correct way to trigger a system reset using the SCB in ARM Cortex-M processors?

easy

A. Toggle the ENABLE bit in the SCB_CCR register

B. Write 0x5FA to the AIRCR register's VECTKEY field and set SYSRESETREQ bit

C. Write 0xA5 to the SCR register

D. Set the RESET bit in the NVIC register

Solution

1. Step 1: Identify the reset trigger method in SCB

   To trigger a system reset, the AIRCR (Application Interrupt and Reset Control Register) requires writing the key 0x5FA to the VECTKEY field and setting the SYSRESETREQ bit.

2. Step 2: Verify other options

   NVIC does not have a RESET bit; SCR and CCR registers do not control reset directly.

3. Final Answer:

   Write 0x5FA to the AIRCR register's VECTKEY field and set SYSRESETREQ bit -> Option B

4. Quick Check:

   Reset = AIRCR key 0x5FA + SYSRESETREQ [OK]

Hint: Use AIRCR with key 0x5FA and SYSRESETREQ to reset [OK]

Common Mistakes:

• Writing wrong key to AIRCR
• Trying to reset via NVIC or SCR registers
• Not setting SYSRESETREQ bit

3. Given the following code snippet accessing SCB registers in ARM Cortex-M, what will be the output?

uint32_t reset_cause = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
printf("Active vector: %lu\n", reset_cause);

medium

A. The system reset cause code

B. The current processor mode

C. The active interrupt vector number

D. A compilation error due to wrong register

Solution

1. Step 1: Understand the ICSR register and VECTACTIVE field

   The ICSR (Interrupt Control and State Register) contains the VECTACTIVE field which holds the number of the currently active interrupt vector.

2. Step 2: Analyze the code operation

   The code masks ICSR with VECTACTIVE_Msk to extract the active vector number and prints it as an unsigned long integer.

3. Final Answer:

   The active interrupt vector number -> Option C

4. Quick Check:

   ICSR & VECTACTIVE = active vector number [OK]

Hint: ICSR VECTACTIVE field shows active interrupt vector [OK]

Common Mistakes:

• Confusing active vector with reset cause
• Assuming compilation error due to register access
• Thinking it shows processor mode

4. A developer tries to configure the SCB to enable divide-by-zero trap by writing:

SCB->CCR |= (1 << 4);

but the trap does not activate. What is the likely issue?

medium

A. The SCB registers are read-only and cannot be changed

B. Bit 4 in CCR is reserved and cannot be set

C. The CCR register requires a write key before modification

D. The divide-by-zero trap enable bit is bit 3, not bit 4

Solution

1. Step 1: Identify the correct bit for divide-by-zero trap in CCR

   In the SCB_CCR register, the divide-by-zero trap enable bit is bit 3, not bit 4.

2. Step 2: Understand the effect of setting wrong bit

   Setting bit 4 has no effect because it is not assigned to enable the divide-by-zero trap.

3. Final Answer:

   The divide-by-zero trap enable bit is bit 3, not bit 4 -> Option D

4. Quick Check:

   Divide-by-zero trap = CCR bit 3 [OK]

Hint: Check exact bit number for trap enable in CCR [OK]

Common Mistakes:

• Setting wrong bit in CCR
• Assuming write key needed for CCR
• Thinking SCB registers are read-only

5. You want to configure the SCB to prioritize system handlers and enable fault exceptions only when the processor is in privileged mode. Which combination of SCB registers and bits should you set?

hard

A. Set SHPR registers to assign priority and set the PRIGROUP field in AIRCR; enable FAULTMASK for privileged faults

B. Set SCR register's SLEEPONEXIT bit and clear PRIGROUP in AIRCR

C. Write 0x5FA to AIRCR and set the VECTRESET bit

D. Enable interrupts in NVIC and disable FAULTMASK

Solution

1. Step 1: Prioritize system handlers using SHPR and AIRCR

   System Handler Priority Registers (SHPR) set priorities for system exceptions. The AIRCR register's PRIGROUP field controls priority grouping.

2. Step 2: Enable fault exceptions only in privileged mode using FAULTMASK

   FAULTMASK register masks fault exceptions in unprivileged mode, allowing faults only in privileged mode.

3. Final Answer:

   Set SHPR registers to assign priority and set the PRIGROUP field in AIRCR; enable FAULTMASK for privileged faults -> Option A

4. Quick Check:

   SHPR + AIRCR PRIGROUP + FAULTMASK = prioritized privileged faults [OK]

Hint: Use SHPR, AIRCR PRIGROUP, and FAULTMASK for privileged fault control [OK]

Common Mistakes:

• Confusing SCR bits with priority control
• Using VECTRESET for priority settings
• Ignoring FAULTMASK role in privilege filtering