SCB (System Control Block) in ARM Architecture - Time & Space Complexity

Time Complexity: SCB (System Control Block)

O(N)

Understanding Time Complexity

When working with the System Control Block (SCB) in ARM architecture, it is important to understand how the time to access or modify its registers grows as the number of operations increases.

We want to know how the execution time changes when we perform multiple SCB register reads or writes.

Scenario Under Consideration

Analyze the time complexity of the following ARM assembly code snippet that reads and writes SCB registers in a loop.

    MOV R0, #0          ; Initialize counter
loop:
    LDR R1, [SCB_BASE, #OFFSET]  ; Read SCB register
    STR R1, [SCB_BASE, #OFFSET]  ; Write back to SCB register
    ADD R0, R0, #1      ; Increment counter
    CMP R0, #N          ; Compare with N
    BLT loop            ; Loop if R0 < N
    

This code reads and writes a SCB register N times in a loop.

Identify Repeating Operations

In this code, the main repeating operations are:

• Primary operation: Reading and writing the SCB register inside the loop.
• How many times: Exactly N times, controlled by the loop counter.

How Execution Grows With Input

As the number N increases, the number of read and write operations to the SCB registers grows linearly.

Input Size (N)	Approx. Operations
10	20 (10 reads + 10 writes)
100	200 (100 reads + 100 writes)
1000	2000 (1000 reads + 1000 writes)

Pattern observation: The total operations double the input size because each iteration does one read and one write.

Final Time Complexity

Time Complexity: O(N)

This means the time to complete the operations grows directly in proportion to the number of iterations N.

Common Mistake

[X] Wrong: "Accessing SCB registers is instantaneous and does not affect execution time regardless of how many times it happens."

[OK] Correct: Each read or write to SCB registers takes processor cycles, so doing it many times adds up and increases total execution time linearly.

Interview Connect

Understanding how repeated hardware register accesses affect execution time helps you reason about low-level system performance and write efficient embedded code.

Self-Check

What if we replaced the loop with a single bulk operation that reads and writes multiple SCB registers at once? How would the time complexity change?

Practice

1. What is the primary role of the System Control Block (SCB) in ARM processors?

easy

A. Manage system-level control and handle exceptions

B. Store user application data

C. Control input/output peripherals

D. Manage memory allocation for programs

Solution

1. Step 1: Understand SCB's function in ARM

   The SCB is designed to manage system-level control tasks and handle exceptions such as faults and interrupts.

2. Step 2: Differentiate SCB from other components

   Unlike memory or peripheral controllers, SCB focuses on system control and exception handling.

3. Final Answer:

   Manage system-level control and handle exceptions -> Option A

4. Quick Check:

   SCB = system control and exceptions [OK]

Hint: SCB controls system and exceptions, not user data [OK]

Common Mistakes:

• Confusing SCB with peripheral controllers
• Thinking SCB manages user data
• Assuming SCB handles memory allocation

2. Which of the following is the correct way to trigger a system reset using the SCB in ARM Cortex-M processors?

easy

A. Toggle the ENABLE bit in the SCB_CCR register

B. Write 0x5FA to the AIRCR register's VECTKEY field and set SYSRESETREQ bit

C. Write 0xA5 to the SCR register

D. Set the RESET bit in the NVIC register

Solution

1. Step 1: Identify the reset trigger method in SCB

   To trigger a system reset, the AIRCR (Application Interrupt and Reset Control Register) requires writing the key 0x5FA to the VECTKEY field and setting the SYSRESETREQ bit.

2. Step 2: Verify other options

   NVIC does not have a RESET bit; SCR and CCR registers do not control reset directly.

3. Final Answer:

   Write 0x5FA to the AIRCR register's VECTKEY field and set SYSRESETREQ bit -> Option B

4. Quick Check:

   Reset = AIRCR key 0x5FA + SYSRESETREQ [OK]

Hint: Use AIRCR with key 0x5FA and SYSRESETREQ to reset [OK]

Common Mistakes:

• Writing wrong key to AIRCR
• Trying to reset via NVIC or SCR registers
• Not setting SYSRESETREQ bit

3. Given the following code snippet accessing SCB registers in ARM Cortex-M, what will be the output?

uint32_t reset_cause = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
printf("Active vector: %lu\n", reset_cause);

medium

A. The system reset cause code

B. The current processor mode

C. The active interrupt vector number

D. A compilation error due to wrong register

Solution

1. Step 1: Understand the ICSR register and VECTACTIVE field

   The ICSR (Interrupt Control and State Register) contains the VECTACTIVE field which holds the number of the currently active interrupt vector.

2. Step 2: Analyze the code operation

   The code masks ICSR with VECTACTIVE_Msk to extract the active vector number and prints it as an unsigned long integer.

3. Final Answer:

   The active interrupt vector number -> Option C

4. Quick Check:

   ICSR & VECTACTIVE = active vector number [OK]

Hint: ICSR VECTACTIVE field shows active interrupt vector [OK]

Common Mistakes:

• Confusing active vector with reset cause
• Assuming compilation error due to register access
• Thinking it shows processor mode

4. A developer tries to configure the SCB to enable divide-by-zero trap by writing:

SCB->CCR |= (1 << 4);

but the trap does not activate. What is the likely issue?

medium

A. The SCB registers are read-only and cannot be changed

B. Bit 4 in CCR is reserved and cannot be set

C. The CCR register requires a write key before modification

D. The divide-by-zero trap enable bit is bit 3, not bit 4

Solution

1. Step 1: Identify the correct bit for divide-by-zero trap in CCR

   In the SCB_CCR register, the divide-by-zero trap enable bit is bit 3, not bit 4.

2. Step 2: Understand the effect of setting wrong bit

   Setting bit 4 has no effect because it is not assigned to enable the divide-by-zero trap.

3. Final Answer:

   The divide-by-zero trap enable bit is bit 3, not bit 4 -> Option D

4. Quick Check:

   Divide-by-zero trap = CCR bit 3 [OK]

Hint: Check exact bit number for trap enable in CCR [OK]

Common Mistakes:

• Setting wrong bit in CCR
• Assuming write key needed for CCR
• Thinking SCB registers are read-only

5. You want to configure the SCB to prioritize system handlers and enable fault exceptions only when the processor is in privileged mode. Which combination of SCB registers and bits should you set?

hard

A. Set SHPR registers to assign priority and set the PRIGROUP field in AIRCR; enable FAULTMASK for privileged faults

B. Set SCR register's SLEEPONEXIT bit and clear PRIGROUP in AIRCR

C. Write 0x5FA to AIRCR and set the VECTRESET bit

D. Enable interrupts in NVIC and disable FAULTMASK

Solution

1. Step 1: Prioritize system handlers using SHPR and AIRCR

   System Handler Priority Registers (SHPR) set priorities for system exceptions. The AIRCR register's PRIGROUP field controls priority grouping.

2. Step 2: Enable fault exceptions only in privileged mode using FAULTMASK

   FAULTMASK register masks fault exceptions in unprivileged mode, allowing faults only in privileged mode.

3. Final Answer:

   Set SHPR registers to assign priority and set the PRIGROUP field in AIRCR; enable FAULTMASK for privileged faults -> Option A

4. Quick Check:

   SHPR + AIRCR PRIGROUP + FAULTMASK = prioritized privileged faults [OK]

Hint: Use SHPR, AIRCR PRIGROUP, and FAULTMASK for privileged fault control [OK]

Common Mistakes:

• Confusing SCR bits with priority control
• Using VECTRESET for priority settings
• Ignoring FAULTMASK role in privilege filtering