SCB (System Control Block) in ARM Architecture - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to access the SCB register that holds the CPU ID.

ARM Architecture

cpu_id = SCB->[1];

Drag options to blanks, or click blank then click option'

ACPUID

BVTOR

CAIRCR

DSCR

Attempts:

3 left

💡 Hint

Common Mistakes

Using VTOR which is for vector table offset.

Using AIRCR which is for application interrupt control.

The CPUID register in the SCB holds the CPU identification information.

2fill in blank

medium

Complete the code to set the vector table offset in the SCB.

ARM Architecture

SCB->[1] = vector_table_address;

Drag options to blanks, or click blank then click option'

ASCR

BCCR

CVTOR

DCPUID

Attempts:

3 left

💡 Hint

Common Mistakes

Using CPUID which is for CPU identification.

Using SCR which controls sleep behavior.

The VTOR register in the SCB is used to set the vector table offset address.

3fill in blank

hard

Fix the error in the code to trigger a system reset using the SCB.

ARM Architecture

SCB->[1] = (0x5FA << 16) | (1 << 2);

Drag options to blanks, or click blank then click option'

AAIRCR

BCPUID

CVTOR

DSCR

Attempts:

3 left

💡 Hint

Common Mistakes

Using CPUID which is read-only.

Using VTOR which sets vector table offset.

The AIRCR register is used to request a system reset by writing the key (0x5FA) and setting the SYSRESETREQ bit (bit 2).

4fill in blank

hard

Fill both blanks to enable deep sleep and set sleep on exit in the SCB.

ARM Architecture

SCB->[1] |= (1 << 2);
SCB->[2] |= (1 << 1);

Drag options to blanks, or click blank then click option'

ASCR

BAIRCR

CCCR

DVTOR

Attempts:

3 left

💡 Hint

Common Mistakes

Using AIRCR which is for interrupts and resets.

Using CCR which controls configuration but not sleep.

The SCR (System Control Register) controls sleep behavior. Bit 2 enables deep sleep, and bit 1 enables sleep on exit.

5fill in blank

hard

Fill all three blanks to create a dictionary comprehension that maps SCB register names to their reset values if the reset value is greater than zero.

ARM Architecture

reset_values = { [1]: [2] for [1] in scb_registers if [2] > 0 }

Drag options to blanks, or click blank then click option'

Areg

Bvalue

C>

Dscb_registers

Attempts:

3 left

💡 Hint

Common Mistakes

Using the collection name as a key or value.

Using incorrect comparison operators.

This comprehension creates a dictionary where keys are register names (reg) and values are their reset values (value), including only those with reset values greater than zero.

Practice

1. What is the primary role of the System Control Block (SCB) in ARM processors?

easy

A. Manage system-level control and handle exceptions

B. Store user application data

C. Control input/output peripherals

D. Manage memory allocation for programs

Solution

1. Step 1: Understand SCB's function in ARM

   The SCB is designed to manage system-level control tasks and handle exceptions such as faults and interrupts.

2. Step 2: Differentiate SCB from other components

   Unlike memory or peripheral controllers, SCB focuses on system control and exception handling.

3. Final Answer:

   Manage system-level control and handle exceptions -> Option A

4. Quick Check:

   SCB = system control and exceptions [OK]

Hint: SCB controls system and exceptions, not user data [OK]

Common Mistakes:

• Confusing SCB with peripheral controllers
• Thinking SCB manages user data
• Assuming SCB handles memory allocation

2. Which of the following is the correct way to trigger a system reset using the SCB in ARM Cortex-M processors?

easy

A. Toggle the ENABLE bit in the SCB_CCR register

B. Write 0x5FA to the AIRCR register's VECTKEY field and set SYSRESETREQ bit

C. Write 0xA5 to the SCR register

D. Set the RESET bit in the NVIC register

Solution

1. Step 1: Identify the reset trigger method in SCB

   To trigger a system reset, the AIRCR (Application Interrupt and Reset Control Register) requires writing the key 0x5FA to the VECTKEY field and setting the SYSRESETREQ bit.

2. Step 2: Verify other options

   NVIC does not have a RESET bit; SCR and CCR registers do not control reset directly.

3. Final Answer:

   Write 0x5FA to the AIRCR register's VECTKEY field and set SYSRESETREQ bit -> Option B

4. Quick Check:

   Reset = AIRCR key 0x5FA + SYSRESETREQ [OK]

Hint: Use AIRCR with key 0x5FA and SYSRESETREQ to reset [OK]

Common Mistakes:

• Writing wrong key to AIRCR
• Trying to reset via NVIC or SCR registers
• Not setting SYSRESETREQ bit

3. Given the following code snippet accessing SCB registers in ARM Cortex-M, what will be the output?

uint32_t reset_cause = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
printf("Active vector: %lu\n", reset_cause);

medium

A. The system reset cause code

B. The current processor mode

C. The active interrupt vector number

D. A compilation error due to wrong register

Solution

1. Step 1: Understand the ICSR register and VECTACTIVE field

   The ICSR (Interrupt Control and State Register) contains the VECTACTIVE field which holds the number of the currently active interrupt vector.

2. Step 2: Analyze the code operation

   The code masks ICSR with VECTACTIVE_Msk to extract the active vector number and prints it as an unsigned long integer.

3. Final Answer:

   The active interrupt vector number -> Option C

4. Quick Check:

   ICSR & VECTACTIVE = active vector number [OK]

Hint: ICSR VECTACTIVE field shows active interrupt vector [OK]

Common Mistakes:

• Confusing active vector with reset cause
• Assuming compilation error due to register access
• Thinking it shows processor mode

4. A developer tries to configure the SCB to enable divide-by-zero trap by writing:

SCB->CCR |= (1 << 4);

but the trap does not activate. What is the likely issue?

medium

A. The SCB registers are read-only and cannot be changed

B. Bit 4 in CCR is reserved and cannot be set

C. The CCR register requires a write key before modification

D. The divide-by-zero trap enable bit is bit 3, not bit 4

Solution

1. Step 1: Identify the correct bit for divide-by-zero trap in CCR

   In the SCB_CCR register, the divide-by-zero trap enable bit is bit 3, not bit 4.

2. Step 2: Understand the effect of setting wrong bit

   Setting bit 4 has no effect because it is not assigned to enable the divide-by-zero trap.

3. Final Answer:

   The divide-by-zero trap enable bit is bit 3, not bit 4 -> Option D

4. Quick Check:

   Divide-by-zero trap = CCR bit 3 [OK]

Hint: Check exact bit number for trap enable in CCR [OK]

Common Mistakes:

• Setting wrong bit in CCR
• Assuming write key needed for CCR
• Thinking SCB registers are read-only

5. You want to configure the SCB to prioritize system handlers and enable fault exceptions only when the processor is in privileged mode. Which combination of SCB registers and bits should you set?

hard

A. Set SHPR registers to assign priority and set the PRIGROUP field in AIRCR; enable FAULTMASK for privileged faults

B. Set SCR register's SLEEPONEXIT bit and clear PRIGROUP in AIRCR

C. Write 0x5FA to AIRCR and set the VECTRESET bit

D. Enable interrupts in NVIC and disable FAULTMASK

Solution

1. Step 1: Prioritize system handlers using SHPR and AIRCR

   System Handler Priority Registers (SHPR) set priorities for system exceptions. The AIRCR register's PRIGROUP field controls priority grouping.

2. Step 2: Enable fault exceptions only in privileged mode using FAULTMASK

   FAULTMASK register masks fault exceptions in unprivileged mode, allowing faults only in privileged mode.

3. Final Answer:

   Set SHPR registers to assign priority and set the PRIGROUP field in AIRCR; enable FAULTMASK for privileged faults -> Option A

4. Quick Check:

   SHPR + AIRCR PRIGROUP + FAULTMASK = prioritized privileged faults [OK]

Hint: Use SHPR, AIRCR PRIGROUP, and FAULTMASK for privileged fault control [OK]

Common Mistakes:

• Confusing SCR bits with priority control
• Using VECTRESET for priority settings
• Ignoring FAULTMASK role in privilege filtering