Why bus architecture affects system performance in ARM Architecture - Performance Analysis

Time Complexity: Why bus architecture affects system performance

O(n)

Understanding Time Complexity

Bus architecture plays a key role in how fast a system can move data between parts like the CPU and memory.

We want to understand how the design of the bus affects the time it takes to complete tasks as the system works with more data.

Scenario Under Consideration

Analyze the time complexity of this simple ARM bus data transfer sequence.

LDR R0, [R1]      // Load data from memory address in R1
STR R0, [R2]      // Store data to memory address in R2
ADD R1, R1, #4    // Move to next memory address
ADD R2, R2, #4    // Move to next memory address
SUBS R3, R3, #1   // Decrement counter
BNE loop_start    // Repeat if counter not zero
    

This code copies a block of data from one memory area to another using the system bus repeatedly.

Identify Repeating Operations

Look at what repeats as the data block is copied.

• Primary operation: Loading and storing data over the bus.
• How many times: Once for each data unit in the block (loop count).

How Execution Grows With Input

As the amount of data to copy grows, the number of bus transfers grows too.

Input Size (n)	Approx. Operations
10	20 bus transfers (10 loads + 10 stores)
100	200 bus transfers
1000	2000 bus transfers

Pattern observation: The number of bus operations grows directly with the size of data to move.

Final Time Complexity

Time Complexity: O(n)

This means the time to complete the data transfer grows in a straight line as the data size increases.

Common Mistake

[X] Wrong: "Bus speed does not affect overall system speed because the CPU is fast enough."

[OK] Correct: Even if the CPU is fast, slow bus transfers can cause waiting, slowing down the whole system.

Interview Connect

Understanding how bus design impacts performance helps you explain system bottlenecks clearly and shows you grasp hardware-software interaction.

Self-Check

"What if the bus width doubled, allowing twice as much data per transfer? How would the time complexity change?"