DMA controller on bus in ARM Architecture - Step-by-Step Execution

Concept Flow - DMA controller on bus

CPU initiates DMA

↓

DMA Controller requests bus

↓

Bus arbiter grants bus to DMA

↓

DMA transfers data directly

↓

DMA signals completion

↓

CPU resumes control

The CPU starts the DMA transfer, the DMA controller requests and gains control of the bus, transfers data directly, then signals completion to the CPU.

Execution Sample

ARM Architecture

CPU sets DMA start
DMA requests bus
Bus arbiter grants bus
DMA transfers data
DMA signals done
CPU resumes

This sequence shows how the DMA controller takes control of the bus to transfer data without CPU intervention.

Analysis Table

Step	Action	Bus Status	Controller Active	CPU Status	Result
1	CPU sets DMA start	Bus with CPU	Inactive	Active	DMA ready to request bus
2	DMA requests bus	Bus with CPU	Requesting	Active	DMA waits for bus grant
3	Bus arbiter grants bus to DMA	Bus with DMA	Active	Paused	DMA gains bus control
4	DMA transfers data	Bus with DMA	Active	Paused	Data moves directly between memory and device
5	DMA signals completion	Bus with DMA	Active	Paused	DMA finished transfer
6	CPU resumes control	Bus with CPU	Inactive	Active	CPU regains bus control
7	End	Bus with CPU	Inactive	Active	DMA transfer complete, CPU continues

💡 DMA transfer ends when CPU regains bus control after DMA signals completion

State Tracker

Variable	Start	After Step 2	After Step 3	After Step 5	Final
Bus Control	CPU	CPU	DMA	DMA	CPU
DMA Controller	Inactive	Requesting	Active	Active	Inactive
CPU	Active	Active	Paused	Paused	Active

Key Insights - 3 Insights

Why does the CPU pause during DMA transfer?

Because the bus arbiter grants control of the bus to the DMA controller (see execution_table step 3), the CPU must wait until DMA finishes.

How does DMA transfer data without CPU intervention?

Once DMA has bus control (step 4), it directly moves data between memory and device, bypassing the CPU.

What signals the CPU to resume control?

The DMA controller signals completion (step 5), after which the bus arbiter returns control to the CPU (step 6).

Visual Quiz - 3 Questions

At which step does the DMA controller gain control of the bus?

A Step 3

B Step 2

C Step 4

D Step 5

💡 Hint

Check the 'Bus Status' and 'Controller Active' columns in execution_table at each step.

What is the CPU status during the DMA data transfer?

A Requesting bus

B Paused

C Active

D Idle

💡 Hint

Look at the 'CPU Status' column in execution_table during step 4.

If the bus arbiter never grants the bus to DMA, what happens?

A DMA transfers data anyway

B CPU pauses indefinitely

C DMA waits and CPU continues

D DMA signals completion immediately

💡 Hint

Refer to execution_table steps 2 and 3 about bus granting and CPU status.

Concept Snapshot

DMA Controller on Bus:
- CPU starts DMA transfer
- DMA requests bus control
- Bus arbiter grants bus to DMA
- DMA transfers data directly
- DMA signals completion
- CPU regains bus control

Full Transcript

The DMA controller on the bus works by the CPU first initiating a DMA transfer. Then the DMA controller requests control of the system bus. The bus arbiter decides who controls the bus and grants it to the DMA controller. While the DMA has control, it transfers data directly between memory and the device without CPU involvement. After the transfer completes, the DMA signals the CPU. The bus arbiter then returns control of the bus to the CPU, which resumes normal operation.