Deep sleep mode in ARM Architecture - Time & Space Complexity
We want to understand how the time cost changes when a processor enters deep sleep mode.
Specifically, how the time to wake up or resume work depends on system factors.
Analyze the time complexity of this ARM assembly snippet managing deep sleep:
WFI ; Wait For Interrupt - enters low power state
MOV R0, #1 ; Prepare to resume
BL wake_up ; Branch to wake-up routine
wake_up:
LDR R1, =status
LDR R1, [R1]
CMP R1, #0
BEQ wake_up
BX LR
This code puts the CPU into deep sleep until an interrupt wakes it, then checks a status flag repeatedly.
Look for loops or repeated checks after waking:
- Primary operation: The loop checking the status flag with CMP and BEQ instructions.
- How many times: This loop runs until the status flag changes, which depends on external events.
The time spent looping depends on how long the status flag takes to change.
| Input Size (n) | Approx. Operations |
|---|---|
| 10 (fast flag change) | About 10 checks |
| 100 (slower flag change) | About 100 checks |
| 1000 (very slow flag change) | About 1000 checks |
Pattern observation: The number of operations grows linearly with how long the flag takes to update.
Time Complexity: O(n)
This means the time to fully wake and resume depends directly on how many times the status flag is checked before it changes.
[X] Wrong: "The wake-up time is always constant regardless of status checks."
[OK] Correct: The CPU may loop many times checking the flag, so wake-up time depends on how quickly the flag updates.
Understanding how waiting loops affect time helps you reason about power management and responsiveness in real devices.
"What if the status flag was checked using an interrupt instead of a loop? How would the time complexity change?"