AHB and APB bus overview in ARM Architecture - Time & Space Complexity
We want to understand how the time to transfer data changes when using AHB and APB buses in ARM systems.
How does the bus design affect the speed as data size or requests increase?
Analyze the time complexity of this simplified ARM bus transaction sequence.
// Simplified bus transaction sequence
START:
READ DATA_FROM_AHB
WRITE DATA_TO_APB
CHECK IF MORE_DATA
IF YES: LOOP TO START
ELSE: END
This code shows reading multiple data units from the faster AHB bus and then writing to the slower APB bus.
Look for repeated steps that take most time.
- Primary operation: Loop reading data from AHB bus and writing to APB bus.
- How many times: Once per data unit, depends on data size.
More data means more reads from AHB and writes to APB.
| Input Size (n) | Approx. Operations |
|---|---|
| 10 | About 10 reads + 10 writes |
| 100 | About 100 reads + 100 writes |
| 1000 | About 1000 reads + 1000 writes |
Pattern observation: The total operations grow linearly with the number of data units.
Time Complexity: O(n)
This means the time to complete transfers grows directly in proportion to the amount of data.
[X] Wrong: "The APB bus speed does not affect overall transfer time because it is simpler."
[OK] Correct: APB is slower and each write takes time, so it adds up and affects total time linearly with data size.
Understanding how bus speeds and repeated transfers affect performance helps you explain system bottlenecks clearly and shows you grasp real hardware behavior.
What if the APB bus was replaced with a faster bus? How would the time complexity change?