Formal Verification in Simulink: What It Is and How It Works

Formal verification in Simulink is a method to mathematically prove that a model meets its design requirements without running simulations. It uses model checking to explore all possible states and find errors like deadlocks or violations of safety properties.

How It Works

Formal verification in Simulink works like a very thorough proofreader who checks every possible way your model could behave, not just the examples you test. Instead of running simulations with sample inputs, it uses mathematical logic to explore all possible states and transitions in the model.

Imagine you have a maze and want to be sure there is no way to get stuck or break the rules. Formal verification explores every path in the maze automatically to find any problems. In Simulink, this means checking if your system can ever reach an error state or violate a safety rule.

This process uses model checking tools that translate your Simulink model into a form that can be analyzed mathematically. The tool then searches for counterexamples that prove the model does not meet a requirement. If none are found, the model is formally verified.

Example

This example shows how to set up a simple formal verification check in Simulink using the Simulink Design Verifier to prove that a signal never exceeds a limit.

matlab

model = 'sldemo_fuelsys';
load_system(model);

% Define a property: signal must be less than 1.5
prop = sldvProperty('SignalLimit', 'Signal', 'FuelRate', 'Operator', '<', 'Value', 1.5);

% Run formal analysis
results = sldvModelCheck(model, 'Properties', prop);

% Display results
if results.IsValid
    disp('Property holds: Signal never exceeds 1.5');
else
    disp('Property violated: Counterexample found');
end

close_system(model, 0);

Output

Property holds: Signal never exceeds 1.5

When to Use

Use formal verification in Simulink when you need to be absolutely sure your model meets critical requirements, especially in safety-related systems like automotive, aerospace, or medical devices. It is helpful when simulation alone cannot cover all possible scenarios or inputs.

Formal verification is ideal for detecting hidden errors such as deadlocks, unreachable states, or violations of timing and safety constraints. It complements simulation by providing mathematical proof rather than just testing examples.

For example, if you design a braking system, formal verification can prove that the brake signal will never exceed safe limits under any condition, which is crucial for safety certification.

Key Points

• Formal verification mathematically proves model correctness without simulation.
• It uses model checking to explore all possible states and transitions.
• Helps find errors like deadlocks, unreachable states, and safety violations.
• Best for safety-critical systems requiring high confidence.
• Simulink Design Verifier is the main tool for formal verification in Simulink.

Key Takeaways

Formal verification in Simulink proves model correctness using mathematical analysis, not just simulation.

It explores all possible model behaviors to find errors or prove safety properties.

Use it for safety-critical systems where exhaustive checking is required.

Simulink Design Verifier is the tool that enables formal verification in Simulink.

Formal verification complements simulation by providing proofs instead of test cases.