How to Generate VHDL Code from Simulink Models

To generate VHDL code from a Simulink model, use the HDL Coder toolbox. First, design your model with HDL-compatible blocks, then configure the HDL code generation settings and run the code generation process to produce synthesizable VHDL files.

Syntax

The main steps to generate VHDL code from Simulink are:

• Design Model: Create your algorithm using HDL-compatible blocks in Simulink.
• Set HDL Parameters: Open HDL Workflow Advisor to configure target language (VHDL), synthesis tool, and output folder.
• Run Code Generation: Use the HDL Workflow Advisor or makehdl command to generate VHDL code.

matlab

makehdl('model_name')

Example

This example shows how to generate VHDL code from a simple Simulink model named simple_model using MATLAB commands.

matlab

% Load the Simulink model
load_system('simple_model')

% Generate HDL code (VHDL by default)
makehdl('simple_model')

% Optionally, generate test bench
makehdltb('simple_model')

Output

HDL code generated successfully in the folder 'simple_model_hdl'.
Test bench generated successfully.

Common Pitfalls

• Using unsupported blocks: Some Simulink blocks are not compatible with HDL code generation. Use HDL-compatible blocks or replace unsupported blocks.
• Ignoring fixed-point data types: HDL code generation requires fixed-point or integer data types, not floating-point.
• Not configuring HDL Workflow Advisor: Skipping configuration can cause incorrect code or errors.
• Forgetting to save the model: Always save changes before generating code.

matlab

%% Wrong approach: Using floating-point blocks
% This will cause errors during HDL code generation

% Correct approach: Use fixed-point blocks and data types
% Use Fixed-Point Designer to convert data types

Quick Reference

Summary tips for generating VHDL from Simulink:

• Use HDL Coder toolbox for code generation.
• Design with HDL-compatible blocks and fixed-point data types.
• Configure HDL Workflow Advisor before generating code.
• Use makehdl('model_name') to generate VHDL code programmatically.
• Generate test benches with makehdltb('model_name') for verification.

Key Takeaways

Use HDL Coder toolbox in Simulink to generate synthesizable VHDL code.

Design your model with HDL-compatible blocks and fixed-point data types.

Configure the HDL Workflow Advisor to set target language and synthesis options.

Use makehdl('model_name') command to generate VHDL code programmatically.

Generate test benches with makehdltb('model_name') to verify generated code.