How to Generate Verilog Code from Simulink Models

To generate Verilog code from a Simulink model, use the HDL Coder toolbox. Configure your model for HDL code generation, then use the hdlcoder.Workflow API or the Simulink HDL Code menu to generate synthesizable Verilog code automatically.

Syntax

Use the HDL Coder tools integrated in Simulink to generate Verilog code. The main steps are:

• Configure Model: Set the model's HDL code generation parameters.
• Run Code Generation: Use the hdlcoder.Workflow API or Simulink menus.
• Generate Verilog: The output is synthesizable Verilog files.

Example command syntax in MATLAB to generate HDL code programmatically:

matlab

hdlset_param('model_name', 'TargetLanguage', 'Verilog');
hdlset_param('model_name', 'GenerateHDLTestBench', 'on');
hdlset_param('model_name', 'HDLSubsystem', 'your_subsystem');
hdlcoder.Workflow('model_name').run();

Example

This example shows how to generate Verilog code from a simple Simulink model named simple_model with a subsystem called Subsystem1.

matlab

model = 'simple_model';
load_system(model);
hdlset_param(model, 'TargetLanguage', 'Verilog');
hdlset_param(model, 'GenerateHDLTestBench', 'on');
hdlset_param(model, 'HDLSubsystem', 'Subsystem1');
hdlcoder.Workflow(model).run();
close_system(model, 0);

Output

Simulink model 'simple_model' loaded.
HDL code generation started...
Verilog files generated in the folder 'simple_model_hdl'.
HDL test bench generated.
HDL code generation completed successfully.

Common Pitfalls

• Model Compatibility: Not all Simulink blocks support HDL code generation. Use supported blocks only.
• Subsystem Selection: Specify the correct subsystem for HDL generation; otherwise, code may not generate.
• Parameter Settings: Forgetting to set TargetLanguage to Verilog will generate VHDL or no code.
• Licensing: HDL Coder toolbox is required; without it, code generation will fail.

matlab

%% Wrong way: Missing TargetLanguage setting
hdlset_param('model_name', 'GenerateHDLTestBench', 'on');
hdlcoder.Workflow('model_name').run();

%% Right way: Set TargetLanguage to Verilog
hdlset_param('model_name', 'TargetLanguage', 'Verilog');
hdlset_param('model_name', 'GenerateHDLTestBench', 'on');
hdlcoder.Workflow('model_name').run();

Quick Reference

Step	Description
1. Prepare Model	Use HDL-compatible blocks and create a subsystem for code generation.
2. Set Parameters	Set 'TargetLanguage' to 'Verilog' and enable test bench generation if needed.
3. Run Generation	Use hdlcoder.Workflow or Simulink HDL Code menu to generate code.
4. Review Output	Check generated Verilog files and test benches in the output folder.
5. Fix Issues	Resolve unsupported blocks or parameter errors before regenerating.

Key Takeaways

Use the HDL Coder toolbox in Simulink to generate Verilog code automatically.

Set the 'TargetLanguage' parameter to 'Verilog' before running code generation.

Only HDL-supported blocks and subsystems can be converted to Verilog.

Use the hdlcoder.Workflow API for programmatic and repeatable code generation.

Check generated files and test benches in the output folder after generation.