Design Rules Check (DRC) setup in PCB Design - Cell-by-Cell Formula Trace

Sample Data

This table shows the setup parameters for Design Rules Check (DRC) in a PCB design. It includes minimum clearance between elements, allowed trace widths, and via sizes.

Cell	Value
A1	Rule Name
B1	Minimum Clearance (mm)
C1	Maximum Trace Width (mm)
D1	Minimum Trace Width (mm)
E1	Via Size (mm)
A2	Clearance
B2	0.2
C2
D2
E2
A3	Trace Width
B3
C3	1.0
D3	0.15
E3
A4	Via
B4
C4
D4
E4	0.6

Formula Trace

IF(AND(Clearance >= B2, TraceWidth <= C3, TraceWidth >= D3, ViaSize = E4), "Pass", "Fail")

Step 1: Clearance >= B2

Step 2: TraceWidth <= C3

Step 3: TraceWidth >= D3

Step 4: ViaSize = E4

Step 5: AND(TRUE, TRUE, TRUE, TRUE)

Step 6: IF(TRUE, "Pass", "Fail")

Cell Reference Map

    A       B       C       D       E
1 |Rule Name|MinClr |MaxTrW |MinTrW |ViaSz |
2 |Clearance| 0.2   |       |       |      |
3 |Trace W. |       | 1.0   | 0.15  |      |
4 |Via      |       |       |       | 0.6  |

References used:
- B2 for minimum clearance
- C3 for max trace width
- D3 for min trace width
- E4 for via size

This map shows the cells referenced in the DRC formula for clearance, trace width, and via size rules.

Result

    A       B       C       D       E       F
1 |Rule Name|MinClr |MaxTrW |MinTrW |ViaSz |Result|
2 |Clearance| 0.2   |       |       |      |      |
3 |Trace W. |       | 1.0   | 0.15  |      |      |
4 |Via      |       |       |       | 0.6  |      |
5 |Test Val | 0.25  | 0.5   |       | 0.6  |Pass  |

The 'Result' cell shows 'Pass' because all DRC conditions are met.

The final result cell shows 'Pass' indicating the design meets all the specified rules.

Sheet Trace Quiz - 3 Questions

What does the formula check first in the DRC setup?

A If clearance is at least the minimum required

B If trace width is less than maximum

C If via size matches the required size

D If trace width is greater than minimum

Key Result

IF(AND(condition1, condition2, ..., conditionN), "Pass", "Fail") checks all rules and returns Pass only if all are true.