Dashboard Mode - Design Rules Check (DRC) setup
Goal
Check if the PCB design follows all manufacturing rules to avoid errors before production.
Check if the PCB design follows all manufacturing rules to avoid errors before production.
| Rule Name | Minimum Clearance (mm) | Minimum Trace Width (mm) | Maximum Via Size (mm) | Status |
|---|---|---|---|---|
| Clearance | 0.2 | 0.15 | 0.6 | Pass |
| Trace Width | 0.2 | 0.15 | 0.6 | Pass |
| Via Size | 0.2 | 0.15 | 0.6 | Fail |
| Annular Ring | 0.15 | 0.15 | 0.6 | Pass |
| Component Spacing | 0.25 | 0.15 | 0.6 | Pass |
| Silkscreen Clearance | 0.1 | 0.15 | 0.6 | Pass |
+-----------------------------+ | Total Rules | Passed | Failed | | (KPI) | (KPI) | (KPI) | +-----------------------------+ | Bar Chart: Pass vs Fail | +-------------------------------------+ | Detailed Rules Table | +-------------------------------------+
Filter by Status (Pass/Fail) updates the Bar Chart and Detailed Rules Table to show only selected rules. KPI cards update counts accordingly.
If you filter to show only 'Fail' rules, which components update?
MinTrackWidth = 0.2mmMinClearance = 0.15mmMinHoleSize = 0.3mm. After running DRC, you still see errors for holes sized 0.35mm. What is the most likely cause?MinHoleSize = 0.3mm is correct and DRC tools do check hole sizes, so these are unlikely causes.LayerSpecificClearance = true and set InterLayerClearance = 0.1mm to allow smaller spacing between layers.MinClearance = 0.2mm and enable LayerSpecificClearance = true with InterLayerClearance = 0.1mm -> Option CMinClearance = 0.2mm and enable LayerSpecificClearance = true with InterLayerClearance = 0.1mm [OK]Pass the test and this pattern moves unknown