Memory-to-peripheral transfer in Embedded C - Step-by-Step Execution

Concept Flow - Memory-to-peripheral transfer

Start Transfer

↓

Read Data from Memory

↓

Check Peripheral Ready?

No→Wait

Yes↓

Write Data to Peripheral

↓

More Data?

Yes→Read Data from Memory

No↓

End Transfer

This flow shows reading data from memory, checking if the peripheral is ready, writing data to it, and repeating until all data is sent.

Execution Sample

Embedded C

uint8_t data[] = {10, 20, 30};
for (int i = 0; i < 3; i++) {
  while (!peripheral_ready());
  write_to_peripheral(data[i]);
}

This code sends three bytes from memory to a peripheral, waiting until the peripheral is ready before each write.

Execution Table

Step	i	Condition peripheral_ready()	Action	Data Sent
1	0	True	write_to_peripheral(10)	10
2	1	False	wait	10
3	1	True	write_to_peripheral(20)	20
4	2	True	write_to_peripheral(30)	30
5	3	N/A	End loop	All data sent

💡 i reaches 3, condition i < 3 is False, transfer ends

Variable Tracker

Variable	Start	After 1	After 2	After 3	Final
i	0	1	2	3	3
Data Sent	None	10	20	30	All data sent

Key Moments - 2 Insights

Why do we wait for peripheral_ready() before writing data?

Because the peripheral might not be ready to accept new data immediately. The execution_table rows 2 and 3 show waiting until peripheral_ready() returns True before sending the next byte.

What happens if we don't check peripheral readiness?

Data might be lost or corrupted because the peripheral can't handle new data yet. The loop in the code and the wait action in step 2 prevent this.

Visual Quiz - 3 Questions

Look at the execution_table, what data is sent at step 3?

A 10

B 20

C 30

D None

💡 Hint

Check the 'Data Sent' column at step 3 in the execution_table.

At which step does the peripheral_ready() condition return False?

A Step 4

B Step 1

C Step 2

D Step 5

💡 Hint

Look at the 'Condition peripheral_ready()' column in the execution_table.

If the data array had 4 elements instead of 3, how would the variable 'i' change in variable_tracker?

A It would go up to 4

B It would stay at 3

C It would go up to 5

D It would reset to 0

💡 Hint

The loop runs while i < length of data, so with 4 elements, i increments to 4.

Concept Snapshot

Memory-to-peripheral transfer in embedded C:
- Read data from memory array
- Wait until peripheral is ready
- Write data to peripheral
- Repeat until all data sent
- Prevents data loss by syncing with peripheral readiness

Full Transcript

This visual execution shows how data is transferred from memory to a peripheral device in embedded C. The program reads each byte from a memory array, waits until the peripheral signals it is ready, then writes the byte to the peripheral. This process repeats until all data is sent. The execution table tracks each step, showing the loop index, peripheral readiness check, action taken, and data sent. The variable tracker shows how the loop counter and data sent change over time. Key moments clarify why waiting for peripheral readiness is important to avoid data loss. The quiz tests understanding of the steps and variable changes. This step-by-step trace helps beginners see how memory-to-peripheral transfer works in real embedded code.

Practice

1. What is the main purpose of memory-to-peripheral transfer in embedded systems?

easy

A. To increase the CPU speed during data processing

B. To copy data from one memory location to another memory location

C. To transfer data from a peripheral device back to memory

D. To move data from memory to a device without using the CPU heavily

Solution

1. Step 1: Understand the role of memory-to-peripheral transfer

   This transfer moves data from memory directly to a peripheral device, reducing CPU involvement.

2. Step 2: Compare options with this understanding

   Only To move data from memory to a device without using the CPU heavily correctly describes this purpose; others describe different operations or unrelated concepts.

3. Final Answer:

   To move data from memory to a device without using the CPU heavily -> Option D

4. Quick Check:

   Memory-to-peripheral transfer reduces CPU load = A [OK]

Hint: Memory-to-peripheral means memory to device, not memory to memory [OK]

Common Mistakes:

• Confusing memory-to-peripheral with peripheral-to-memory transfer
• Thinking it increases CPU speed
• Assuming it copies memory internally

2. Which of the following is the correct way to enable memory increment mode in a DMA configuration in embedded C?

easy

A. DMA->CCR &= ~DMA_CCR_MINC;

B. DMA->CCR |= DMA_CCR_MINC;

C. DMA->CCR = DMA_CCR_MINC;

D. DMA->CCR ^= DMA_CCR_MINC;

Solution

1. Step 1: Understand enabling a bit in a register

   To enable memory increment, set the MINC bit using bitwise OR (|=) to keep other bits unchanged.

2. Step 2: Analyze each option

   DMA->CCR |= DMA_CCR_MINC; uses |= which sets the bit correctly. DMA->CCR &= ~DMA_CCR_MINC; clears the bit, C overwrites all bits, D toggles the bit which is unsafe here.

3. Final Answer:

   DMA->CCR |= DMA_CCR_MINC; -> Option B

4. Quick Check:

   Enable bit with |= operator = A [OK]

Hint: Use |= to set bits without changing others [OK]

Common Mistakes:

• Using &= ~ to enable bits (actually disables)
• Assigning directly which clears other bits
• Using ^= which toggles bits unpredictably

3. Given the following code snippet configuring a DMA transfer, what will be the value of the peripheral data register after the transfer completes?

uint16_t data[3] = {10, 20, 30};
DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;
DMA->CNDTR = 3;
DMA->CPAR = (uint32_t)&PERIPH->DR;
DMA->CMAR = (uint32_t)data;
// DMA transfer starts and completes

medium

A. 30

B. 10

C. 20

D. 0

Solution

1. Step 1: Understand memory increment and transfer count

   Memory increment is enabled, so DMA reads data[0], data[1], data[2] sequentially, transferring 3 items.

2. Step 2: Determine final peripheral register value

   Each transfer writes to peripheral register. After last transfer, peripheral data register holds last value transferred: data[2] = 30.

3. Final Answer:

   30 -> Option A

4. Quick Check:

   Last transferred value = 30 [OK]

Hint: Peripheral register ends with last memory value sent [OK]

Common Mistakes:

• Assuming peripheral holds first or middle value
• Ignoring memory increment effect
• Confusing transfer count with data index

4. Identify the error in this DMA memory-to-peripheral transfer setup:

DMA->CCR = DMA_CCR_DIR;
DMA->CNDTR = 5;
DMA->CPAR = (uint32_t)&PERIPH->DR;
DMA->CMAR = (uint32_t)data_array;
// Start DMA transfer

medium

A. Memory increment mode is not enabled, so only first data is sent repeatedly

B. Peripheral address is incorrect, should point to memory

C. Transfer count is set too high causing overflow

D. DMA direction bit is cleared, so transfer is peripheral to memory

Solution

1. Step 1: Check memory increment setting

   DMA_CCR_MINC bit is missing, so memory address does not increment during transfer.

2. Step 2: Understand effect of missing memory increment

   Without memory increment, DMA sends the same memory location repeatedly to peripheral, not the full array.

3. Final Answer:

   Memory increment mode is not enabled, so only first data is sent repeatedly -> Option A

4. Quick Check:

   Missing MINC bit causes repeated data = D [OK]

Hint: Always enable memory increment for multiple data items [OK]

Common Mistakes:

• Assuming peripheral address should point to memory
• Thinking transfer count causes overflow here
• Misreading direction bit status

5. You want to transfer a block of 4 bytes from memory to a UART peripheral using DMA. The memory buffer is at address 0x20001000 and the UART data register is at 0x40013804. Which DMA configuration correctly sets the source, destination, and enables memory increment for this transfer?

Options:
A) DMA->CMAR = 0x20001000; DMA->CPAR = 0x40013804; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;
B) DMA->CPAR = 0x20001000; DMA->CMAR = 0x40013804; DMA->CCR = DMA_CCR_MINC;
C) DMA->CPAR = 0x40013804; DMA->CMAR = 0x20001000; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;
D) DMA->CMAR = 0x40013804; DMA->CPAR = 0x20001000; DMA->CCR = DMA_CCR_DIR;

hard

A. DMA->CPAR = 0x40013804; DMA->CMAR = 0x20001000; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;

B. DMA->CPAR = 0x20001000; DMA->CMAR = 0x40013804; DMA->CCR = DMA_CCR_MINC;

C. DMA->CMAR = 0x20001000; DMA->CPAR = 0x40013804; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;

D. DMA->CMAR = 0x40013804; DMA->CPAR = 0x20001000; DMA->CCR = DMA_CCR_DIR;

Solution

1. Step 1: Identify source and destination addresses

   Memory buffer is source (CMAR), peripheral register is destination (CPAR).

2. Step 2: Check DMA direction and memory increment

   DMA_CCR_DIR set means memory-to-peripheral transfer; DMA_CCR_MINC enables memory address increment.

3. Step 3: Match correct option

   DMA->CMAR = 0x20001000; DMA->CPAR = 0x40013804; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR; correctly assigns CMAR to memory, CPAR to peripheral, and sets both DIR and MINC bits.

4. Final Answer:

   DMA->CMAR = 0x20001000; DMA->CPAR = 0x40013804; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR; -> Option C

5. Quick Check:

   Memory in CMAR, peripheral in CPAR, DIR and MINC set = A [OK]

Hint: Peripheral address in CPAR, memory in CMAR, set DIR and MINC bits [OK]

Common Mistakes:

• Swapping source and destination addresses
• Forgetting to set memory increment bit
• Not setting direction bit for memory-to-peripheral