Memory-to-peripheral transfer in Embedded C - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is Memory-to-peripheral transfer in embedded systems?

It is the process of moving data from the system's memory directly to a hardware peripheral device, often using DMA (Direct Memory Access) to avoid CPU involvement.

beginner

Why use DMA for memory-to-peripheral transfer instead of CPU?

DMA allows data transfer without CPU intervention, freeing the CPU to perform other tasks and improving system efficiency and speed.

intermediate

In embedded C, which peripheral register is typically used to start a memory-to-peripheral DMA transfer?

Usually, a DMA control register or a specific DMA channel configuration register is set to enable and start the transfer.

intermediate

What is the role of the volatile keyword in memory-to-peripheral transfers?

It tells the compiler that the variable can change unexpectedly (e.g., by hardware), so it should not optimize away reads or writes, ensuring correct data transfer.

advanced

Give a simple example of setting up a memory-to-peripheral DMA transfer in embedded C.

Example: Configure DMA source address to memory buffer, destination address to peripheral data register, set transfer size, enable DMA channel, and start transfer.

What does DMA stand for in embedded systems?

A Dynamic Memory Addressing

B Data Memory Allocation

C Device Memory Access

D Direct Memory Access

DMA means Direct Memory Access, a method to transfer data without CPU involvement.

Which is a key benefit of memory-to-peripheral transfer using DMA?

A CPU is free to do other tasks

B Data is encrypted automatically

C Memory size increases

D Peripheral speed decreases

DMA frees the CPU by handling data transfer directly.

In embedded C, why use the volatile keyword for peripheral registers?

A To increase variable size

B To make variables constant

C To prevent compiler optimizations that skip hardware updates

D To speed up the program

Volatile ensures the compiler always reads/writes the variable as it may change unexpectedly.

Which of these is NOT typically involved in memory-to-peripheral DMA setup?

A Source address

B Screen resolution

C Transfer size

D Destination address

Screen resolution is unrelated to DMA transfers.

What triggers the start of a DMA memory-to-peripheral transfer?

A Enabling the DMA channel and setting control bits

B Writing to a file

C Resetting the CPU

D Turning off the peripheral

DMA transfer starts when the DMA channel is enabled and configured.

Explain how memory-to-peripheral transfer works in embedded systems and why DMA is used.

Think about how data moves from memory to devices without CPU help.

Describe the steps to set up a memory-to-peripheral DMA transfer in embedded C.

Consider what registers and configurations are needed before starting the transfer.

Practice

1. What is the main purpose of memory-to-peripheral transfer in embedded systems?

easy

A. To increase the CPU speed during data processing

B. To copy data from one memory location to another memory location

C. To transfer data from a peripheral device back to memory

D. To move data from memory to a device without using the CPU heavily

Solution

1. Step 1: Understand the role of memory-to-peripheral transfer

   This transfer moves data from memory directly to a peripheral device, reducing CPU involvement.

2. Step 2: Compare options with this understanding

   Only To move data from memory to a device without using the CPU heavily correctly describes this purpose; others describe different operations or unrelated concepts.

3. Final Answer:

   To move data from memory to a device without using the CPU heavily -> Option D

4. Quick Check:

   Memory-to-peripheral transfer reduces CPU load = A [OK]

Hint: Memory-to-peripheral means memory to device, not memory to memory [OK]

Common Mistakes:

• Confusing memory-to-peripheral with peripheral-to-memory transfer
• Thinking it increases CPU speed
• Assuming it copies memory internally

2. Which of the following is the correct way to enable memory increment mode in a DMA configuration in embedded C?

easy

A. DMA->CCR &= ~DMA_CCR_MINC;

B. DMA->CCR |= DMA_CCR_MINC;

C. DMA->CCR = DMA_CCR_MINC;

D. DMA->CCR ^= DMA_CCR_MINC;

Solution

1. Step 1: Understand enabling a bit in a register

   To enable memory increment, set the MINC bit using bitwise OR (|=) to keep other bits unchanged.

2. Step 2: Analyze each option

   DMA->CCR |= DMA_CCR_MINC; uses |= which sets the bit correctly. DMA->CCR &= ~DMA_CCR_MINC; clears the bit, C overwrites all bits, D toggles the bit which is unsafe here.

3. Final Answer:

   DMA->CCR |= DMA_CCR_MINC; -> Option B

4. Quick Check:

   Enable bit with |= operator = A [OK]

Hint: Use |= to set bits without changing others [OK]

Common Mistakes:

• Using &= ~ to enable bits (actually disables)
• Assigning directly which clears other bits
• Using ^= which toggles bits unpredictably

3. Given the following code snippet configuring a DMA transfer, what will be the value of the peripheral data register after the transfer completes?

uint16_t data[3] = {10, 20, 30};
DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;
DMA->CNDTR = 3;
DMA->CPAR = (uint32_t)&PERIPH->DR;
DMA->CMAR = (uint32_t)data;
// DMA transfer starts and completes

medium

A. 30

B. 10

C. 20

D. 0

Solution

1. Step 1: Understand memory increment and transfer count

   Memory increment is enabled, so DMA reads data[0], data[1], data[2] sequentially, transferring 3 items.

2. Step 2: Determine final peripheral register value

   Each transfer writes to peripheral register. After last transfer, peripheral data register holds last value transferred: data[2] = 30.

3. Final Answer:

   30 -> Option A

4. Quick Check:

   Last transferred value = 30 [OK]

Hint: Peripheral register ends with last memory value sent [OK]

Common Mistakes:

• Assuming peripheral holds first or middle value
• Ignoring memory increment effect
• Confusing transfer count with data index

4. Identify the error in this DMA memory-to-peripheral transfer setup:

DMA->CCR = DMA_CCR_DIR;
DMA->CNDTR = 5;
DMA->CPAR = (uint32_t)&PERIPH->DR;
DMA->CMAR = (uint32_t)data_array;
// Start DMA transfer

medium

A. Memory increment mode is not enabled, so only first data is sent repeatedly

B. Peripheral address is incorrect, should point to memory

C. Transfer count is set too high causing overflow

D. DMA direction bit is cleared, so transfer is peripheral to memory

Solution

1. Step 1: Check memory increment setting

   DMA_CCR_MINC bit is missing, so memory address does not increment during transfer.

2. Step 2: Understand effect of missing memory increment

   Without memory increment, DMA sends the same memory location repeatedly to peripheral, not the full array.

3. Final Answer:

   Memory increment mode is not enabled, so only first data is sent repeatedly -> Option A

4. Quick Check:

   Missing MINC bit causes repeated data = D [OK]

Hint: Always enable memory increment for multiple data items [OK]

Common Mistakes:

• Assuming peripheral address should point to memory
• Thinking transfer count causes overflow here
• Misreading direction bit status

5. You want to transfer a block of 4 bytes from memory to a UART peripheral using DMA. The memory buffer is at address 0x20001000 and the UART data register is at 0x40013804. Which DMA configuration correctly sets the source, destination, and enables memory increment for this transfer?

Options:
A) DMA->CMAR = 0x20001000; DMA->CPAR = 0x40013804; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;
B) DMA->CPAR = 0x20001000; DMA->CMAR = 0x40013804; DMA->CCR = DMA_CCR_MINC;
C) DMA->CPAR = 0x40013804; DMA->CMAR = 0x20001000; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;
D) DMA->CMAR = 0x40013804; DMA->CPAR = 0x20001000; DMA->CCR = DMA_CCR_DIR;

hard

A. DMA->CPAR = 0x40013804; DMA->CMAR = 0x20001000; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;

B. DMA->CPAR = 0x20001000; DMA->CMAR = 0x40013804; DMA->CCR = DMA_CCR_MINC;

C. DMA->CMAR = 0x20001000; DMA->CPAR = 0x40013804; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;

D. DMA->CMAR = 0x40013804; DMA->CPAR = 0x20001000; DMA->CCR = DMA_CCR_DIR;

Solution

1. Step 1: Identify source and destination addresses

   Memory buffer is source (CMAR), peripheral register is destination (CPAR).

2. Step 2: Check DMA direction and memory increment

   DMA_CCR_DIR set means memory-to-peripheral transfer; DMA_CCR_MINC enables memory address increment.

3. Step 3: Match correct option

   DMA->CMAR = 0x20001000; DMA->CPAR = 0x40013804; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR; correctly assigns CMAR to memory, CPAR to peripheral, and sets both DIR and MINC bits.

4. Final Answer:

   DMA->CMAR = 0x20001000; DMA->CPAR = 0x40013804; DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR; -> Option C

5. Quick Check:

   Memory in CMAR, peripheral in CPAR, DIR and MINC set = A [OK]

Hint: Peripheral address in CPAR, memory in CMAR, set DIR and MINC bits [OK]

Common Mistakes:

• Swapping source and destination addresses
• Forgetting to set memory increment bit
• Not setting direction bit for memory-to-peripheral