Load and store instructions (LDR, STR) in ARM Architecture - Deep Dive

Overview - Load and store instructions (LDR, STR)

What is it?

Load and store instructions in ARM architecture are commands that move data between the processor's registers and memory. LDR (Load Register) reads data from memory into a register, while STR (Store Register) writes data from a register back to memory. These instructions are essential for accessing and modifying data stored outside the processor's immediate registers. They allow the CPU to work with larger amounts of data than it can hold internally.

Why it matters

Without load and store instructions, a processor could only work with data inside its limited registers, severely restricting its ability to handle complex programs or large data sets. These instructions enable efficient data transfer, which is crucial for running software, managing variables, and interacting with hardware. They form the backbone of memory management in ARM processors, impacting everything from simple calculations to advanced applications like operating systems and games.

Where it fits

Before learning load and store instructions, you should understand basic ARM registers and memory concepts. After mastering these instructions, you can explore addressing modes, instruction pipelining, and optimization techniques in ARM assembly programming.

Mental Model

Core Idea

Load and store instructions move data between the CPU's registers and memory to enable processing beyond the CPU's limited internal storage.

Think of it like...

Imagine a kitchen where the chef (CPU) has a small counter (registers) to work on ingredients. The pantry (memory) holds all the food. Load instructions bring ingredients from the pantry to the counter, and store instructions put finished dishes back into the pantry.

┌─────────────┐       LDR        ┌─────────────┐
│   Memory    │ ───────────────▶ │  Register   │
└─────────────┘                  └─────────────┘

┌─────────────┐       STR        ┌─────────────┐
│  Register   │ ───────────────▶ │   Memory    │
└─────────────┘                  └─────────────┘

Build-Up - 6 Steps

1

Foundation

Understanding Registers and Memory

Concept: Registers are small, fast storage locations inside the CPU; memory is larger but slower storage outside the CPU.

Registers hold data the CPU is currently working on. Memory stores data and instructions for longer-term use. The CPU cannot directly perform operations on memory; it must first load data into registers.

Result

You know that registers are limited and memory is larger but slower, setting the stage for why data must move between them.

Understanding the difference between registers and memory is key to grasping why load and store instructions exist.

2

Foundation

Basic Purpose of LDR and STR

Concept: LDR loads data from memory into a register; STR stores data from a register into memory.

LDR reads a value from a memory address and places it into a register. STR takes the value in a register and writes it to a memory address. Both use addresses to specify where data is read or written.

Result

You can identify the direction of data flow for LDR (memory to register) and STR (register to memory).

Knowing the direction of data movement clarifies how the CPU interacts with memory.

3

Intermediate

Addressing Modes in LDR and STR

🤔Before reading on: do you think LDR and STR can only use fixed memory addresses or can they calculate addresses dynamically? Commit to your answer.

Concept: LDR and STR support various addressing modes to calculate memory addresses dynamically using registers and offsets.

Besides fixed addresses, these instructions can use base registers plus immediate offsets, register offsets, or even pre/post indexing to determine the exact memory location. This flexibility allows efficient access to arrays, structures, and stack data.

Result

You understand that load/store instructions can access memory locations calculated at runtime, not just fixed addresses.

Knowing addressing modes reveals how ARM instructions efficiently handle complex data structures.

4

Intermediate

Data Sizes and Alignment

🤔Before reading on: do you think LDR and STR only work with 32-bit data or can they handle different sizes? Commit to your answer.

Concept: LDR and STR can load and store data of different sizes like bytes, halfwords, and words, with alignment rules affecting performance.

ARM instructions include variants like LDRB (load byte) and STRH (store halfword). Proper alignment means data is stored at addresses divisible by its size (e.g., 4 bytes for a word). Misaligned access can cause slower performance or exceptions.

Result

You know how to choose the right instruction for data size and why alignment matters.

Understanding data sizes and alignment helps write efficient and correct ARM code.

5

Advanced

Using LDR and STR with the Stack

🤔Before reading on: do you think LDR and STR can be used to manage the function call stack? Commit to your answer.

Concept: LDR and STR are fundamental for pushing and popping data on the stack during function calls and returns.

The stack is a memory area used to store return addresses, local variables, and saved registers. STR stores registers onto the stack (push), and LDR loads them back (pop). This preserves CPU state across function calls.

Result

You see how load/store instructions enable function call management and local data storage.

Knowing stack operations with LDR/STR is essential for understanding function calls and program flow.

6

Expert

Optimizations and Side Effects in LDR/STR

🤔Before reading on: do you think LDR and STR can modify the base register automatically? Commit to your answer.

Concept: Some LDR and STR variants update the base register automatically (write-back), enabling efficient pointer arithmetic and loop constructs.

Instructions with write-back update the base register after accessing memory, e.g., STR with post-indexing adds an offset to the base register. This reduces extra instructions for pointer updates but requires careful use to avoid bugs.

Result

You understand how write-back addressing optimizes code and the risks involved.

Recognizing write-back behavior helps write compact, efficient code and avoid subtle errors.

Under the Hood

At the hardware level, LDR and STR instructions trigger the CPU's memory management unit to calculate the effective address using the specified addressing mode. For LDR, the data at that address is fetched from memory and loaded into the specified register. For STR, the data in the register is written back to the memory address. These operations involve bus communication between the CPU and memory, and may cause pipeline stalls if the data is not immediately available.

Why designed this way?

ARM was designed for efficiency and flexibility in embedded and general computing. Load/store architecture separates memory access from computation, simplifying instruction design and enabling faster execution. Supporting multiple addressing modes and write-back allows compact code and efficient data handling, which was critical for performance and power consumption in ARM's target devices.

┌───────────────┐
│  CPU Core     │
│ ┌───────────┐ │
│ │ Registers │ │
│ └───────────┘ │
│       │       │
│       ▼       │
│  ┌─────────┐  │
│  │ Address │  │
│  │ Calc.   │  │
│  └─────────┘  │
│       │       │
└───────┼───────┘
        │
        ▼
┌───────────────┐
│   Memory Bus   │
└───────────────┘
        │
        ▼
┌───────────────┐
│    Memory     │
└───────────────┘

Myth Busters - 4 Common Misconceptions

Quick: Does STR copy data from memory to register? Commit yes or no.

Common Belief: STR copies data from memory into a register.

Reality: STR stores data from a register into memory, the opposite direction of LDR.

Why it matters: Confusing STR direction leads to incorrect code that overwrites memory unintentionally or fails to load needed data.

Quick: Can LDR and STR access any memory address without restrictions? Commit yes or no.

Common Belief: LDR and STR can access any memory address freely without alignment or permission issues.

Reality: They require proper alignment and valid memory addresses; misaligned or protected addresses cause faults or slowdowns.

Why it matters: Ignoring alignment can cause program crashes or degraded performance, especially in embedded systems.

Quick: Do LDR and STR instructions always leave the base register unchanged? Commit yes or no.

Common Belief: LDR and STR never modify the base register used for addressing.

Reality: Some variants update the base register automatically (write-back), changing its value after execution.

Why it matters: Not accounting for write-back can cause bugs where pointers unexpectedly change, leading to incorrect memory access.

Quick: Are LDR and STR instructions only used for simple data movement? Commit yes or no.

Common Belief: LDR and STR are only for basic data transfer and have no role in complex operations like stack management.

Reality: They are fundamental for stack operations, function calls, and managing local variables in ARM programs.

Why it matters: Underestimating their role can limit understanding of program flow and debugging complex ARM assembly.

Expert Zone

1

Write-back addressing modes can cause subtle bugs if the base register is used again without realizing it has changed.

2

Using LDR and STR with unaligned addresses may work on some ARM versions but cause unpredictable behavior on others.

3

The pipeline and cache behavior during load/store instructions can affect performance and timing, critical in real-time systems.

When NOT to use

Load/store instructions are not suitable for atomic operations or synchronization; specialized instructions like LDREX/STREX should be used instead. Also, for very small immediate data, MOV instructions are more efficient than loading from memory.

Production Patterns

In real-world ARM software, LDR and STR are heavily used for stack frame setup/teardown, accessing global variables, and manipulating arrays. Compilers optimize their use with addressing modes and write-back to reduce instruction count and improve speed.

Connections

Cache Memory

Load/store instructions interact closely with cache systems to speed up memory access.

Understanding how caches work helps explain why some load/store operations are fast and others cause delays due to cache misses.

Pointer Arithmetic in High-Level Languages

Load/store instructions implement pointer arithmetic and dereferencing at the hardware level.

Knowing how LDR/STR use base registers and offsets clarifies how languages like C access array elements and structures.

Database Read/Write Operations

Both involve moving data between storage and working memory, though at different scales and abstractions.

Recognizing this similarity highlights the universal need to efficiently transfer data between slow storage and fast processing units.

Common Pitfalls

#1 Using STR when intending to load data into a register.

Wrong approach:

STR R0, [R1]

Correct approach:

LDR R0, [R1]

Root cause:

Confusing the direction of data movement between memory and registers.

#2 Ignoring alignment requirements causing faults.

Wrong approach:

LDR R0, [R1, #1] ; address not aligned to 4 bytes

Correct approach:

LDR R0, [R1, #0] ; aligned address

Root cause:

Not understanding that word-sized loads require addresses divisible by 4.

#3 Assuming base register is unchanged after LDR/STR with write-back.

Wrong approach:

STR R0, [R1], #4
; use R1 again assuming same value

Correct approach:

STR R0, [R1], #4
; update code to account for R1 incremented by 4

Root cause:

Not realizing that post-indexing updates the base register automatically.

Key Takeaways

Load (LDR) and store (STR) instructions move data between CPU registers and memory, enabling the processor to work with large data sets.

They support multiple addressing modes, allowing flexible and efficient memory access patterns.

Data size and alignment are critical for correct and efficient load/store operations.

Write-back addressing modes optimize code but require careful handling to avoid bugs.

These instructions are fundamental for stack management, function calls, and overall program flow in ARM architecture.

Practice

1. What does the LDR instruction do in ARM architecture?

easy

A. Stores data from a register into memory

B. Loads data from memory into a register

C. Performs arithmetic operations on registers

D. Jumps to a different instruction address

Solution

1. Step 1: Understand the purpose of LDR

   The LDR instruction is used to read or load data from a memory address into a CPU register.

2. Step 2: Differentiate from STR

   STR is the opposite; it stores data from a register back into memory.

3. Final Answer:

   Loads data from memory into a register -> Option B

4. Quick Check:

   LDR = Load from memory [OK]

Hint: LDR loads from memory, STR stores to memory [OK]

Common Mistakes:

• Confusing LDR with STR
• Thinking LDR performs arithmetic
• Assuming LDR changes program flow

2. Which of the following is the correct syntax to store the value of register R1 into the memory address pointed by R0?

easy

A. STR R0, [R1]

B. LDR R1, [R0]

C. STR R1, [R0]

D. LDR R0, [R1]

Solution

1. Step 1: Identify the store instruction

   STR is used to store data from a register into memory.

2. Step 2: Match registers to syntax

   STR R1, [R0] means store the value in R1 into the memory address held in R0.

3. Final Answer:

   STR R1, [R0] -> Option C

4. Quick Check:

   STR stores register to memory [OK]

Hint: STR stores register to memory address in brackets [OK]

Common Mistakes:

• Swapping register and address in syntax
• Using LDR instead of STR for storing
• Confusing source and destination registers

3. Given the following ARM instructions:

STR R2, [R3]
LDR R4, [R3]

What will be the value in register R4 after execution if R2 = 10 and the memory at address in R3 initially contains 5?

medium

A. 10

B. 5

C. Undefined

D. 0

Solution

1. Step 1: Execute STR instruction

   STR R2, [R3] stores the value 10 (from R2) into the memory address pointed by R3, replacing the initial 5.

2. Step 2: Execute LDR instruction

   LDR R4, [R3] loads the updated memory value (now 10) into R4.

3. Final Answer:

   10 -> Option A

4. Quick Check:

   Store then load updates R4 to 10 [OK]

Hint: Store first, then load from same address updates register [OK]

Common Mistakes:

• Assuming memory value stays 5 after STR
• Confusing source and destination registers
• Ignoring instruction order

4. Identify the error in the following ARM assembly snippet:

LDR R1, R2
STR R3, [R4]

medium

A. LDR syntax is incorrect; missing brackets around R2

B. STR syntax is incorrect; missing brackets around R3

C. Both instructions are correct

D. LDR should use STR instead

Solution

1. Step 1: Check LDR syntax

   LDR loads from memory address, so the source must be in brackets like [R2]. Here, R2 is missing brackets, so syntax is wrong.

2. Step 2: Check STR syntax

   STR R3, [R4] is correct because it stores R3's value into memory at address in R4.

3. Final Answer:

   LDR syntax is incorrect; missing brackets around R2 -> Option A

4. Quick Check:

   LDR needs brackets for memory address [OK]

Hint: LDR and STR need brackets for memory addresses [OK]

Common Mistakes:

• Omitting brackets for memory operands
• Confusing register direct with memory access
• Thinking STR needs brackets on source register

5. You want to copy a block of 4 words from memory starting at address in R5 to another location starting at address in R6 using ARM instructions. Which sequence correctly uses LDR and STR to achieve this?

hard

A. Use LDR R0, [R5, #4]; STR R0, [R6, #4] once

B. Use LDR R0, [R5]; STR R0, [R6] once only

C. Use STR R0, [R5]; LDR R0, [R6] repeated 4 times

D. Use a loop: LDR R0, [R5], #4; STR R0, [R6], #4 repeated 4 times

Solution

1. Step 1: Understand block copy requirement

   Copying 4 words means loading each word from source and storing it to destination, advancing addresses each time.

2. Step 2: Analyze Use a loop: LDR R0, [R5], #4; STR R0, [R6], #4 repeated 4 times

   Use a loop: LDR R0, [R5], #4; STR R0, [R6], #4 repeated 4 times uses LDR and STR with post-increment addressing ([R5], #4 and [R6], #4) inside a loop repeated 4 times, correctly copying each word and moving pointers.

3. Step 3: Analyze other options

   Use LDR R0, [R5]; STR R0, [R6] once only copies only one word. Use STR R0, [R5]; LDR R0, [R6] repeated 4 times reverses load/store roles. Use LDR R0, [R5, #4]; STR R0, [R6, #4] once copies only one word with offset but no loop.

4. Final Answer:

   Use a loop: LDR R0, [R5], #4; STR R0, [R6], #4 repeated 4 times -> Option D

5. Quick Check:

   Loop with LDR/STR and address increment copies block [OK]

Hint: Use loop with LDR/STR and post-increment for block copy [OK]

Common Mistakes:

• Copying only one word instead of all 4
• Mixing load and store instructions
• Not incrementing addresses after each word