Complete the code to identify the core register used for the program counter in ARM Cortex-M.
The program counter register in ARM Cortex-M is called [1].
The program counter (PC) holds the address of the next instruction to execute in ARM Cortex-M processors.
Complete the sentence to describe the main purpose of the NVIC in ARM Cortex-M.
The NVIC in ARM Cortex-M is responsible for managing [1].
The Nested Vectored Interrupt Controller (NVIC) manages interrupts, allowing the processor to respond quickly to events.
Fix the error in the description of the ARM Cortex-M pipeline stages.
The ARM Cortex-M pipeline has three stages: fetch, decode, and [1].
The three pipeline stages are fetch, decode, and execute. Store and writeback are parts of execute or memory stages in other architectures.
Fill both blanks to complete the description of the ARM Cortex-M exception model.
When an exception occurs, the processor saves the [1] and [2] registers automatically.
During an exception, the processor automatically saves the Program Counter (PC) and Program Status Register (PSR) to preserve the execution state.
Fill all three blanks to complete the dictionary comprehension that maps exception names to their priority levels in ARM Cortex-M.
exception_priority = [1]: [2] for [3] in exceptions
This comprehension creates a dictionary where each exception name (exc) maps to its priority value (priority) by iterating over the list exceptions.
