Design for testability (DFT) in PCB Design - Real Business Scenario

Scenario Mode

👤 Your Role: You are a PCB design engineer working with the quality assurance team.

📋 Request: Your manager wants a report showing how well the current PCB designs follow Design for Testability (DFT) principles to reduce manufacturing defects.

📊 Data: You have data on multiple PCB designs including test points count, boundary scan usage, test coverage percentage, and defect rates.

🎯 Deliverable: Create a dashboard that visualizes DFT metrics per design and highlights designs with low test coverage and high defect rates.

Sample Data

Design_ID	Test_Points	Boundary_Scan	Test_Coverage_%	Defect_Rate_%
PCB001	15	Yes	85	2.5
PCB002	8	No	60	7.0
PCB003	20	Yes	90	1.0
PCB004	5	No	50	8.5
PCB005	12	Yes	80	3.0
PCB006	7	No	55	6.5
PCB007	18	Yes	88	2.0
PCB008	6	No	58	7.5

1

Step 1: Load the PCB design data into your BI tool.

Import the table with columns: Design_ID, Test_Points, Boundary_Scan, Test_Coverage_%, Defect_Rate_%

Expected Result

Data table with 8 PCB designs loaded successfully.

2

Step 2: Create a calculated measure 'Low_Test_Coverage' to flag designs with test coverage below 70%.

Low_Test_Coverage = IF([Test_Coverage_%] < 70, "Yes", "No")

Expected Result

Designs PCB002, PCB004, PCB006, and PCB008 flagged as 'Yes' for low test coverage.

3

Step 3: Create a calculated measure 'High_Defect_Rate' to flag designs with defect rate above 5%.

High_Defect_Rate = IF([Defect_Rate_%] > 5, "Yes", "No")

Expected Result

Designs PCB002, PCB004, PCB006, and PCB008 flagged as 'Yes' for high defect rate.

4

Step 4: Build a table visualization showing Design_ID, Test_Points, Boundary_Scan, Test_Coverage_%, Defect_Rate_%, Low_Test_Coverage, High_Defect_Rate.

Configure table with mentioned columns and calculated measures.

Expected Result

Table clearly shows which designs have low test coverage and high defect rates.

5

Step 5: Create a bar chart showing Test_Coverage_% per Design_ID with a color code: red for coverage below 70%, green otherwise.

Set conditional formatting on bars based on Test_Coverage_% threshold 70%.

Expected Result

Bar chart visually highlights designs with insufficient test coverage.

6

Step 6: Create a scatter plot with Test_Coverage_% on X-axis and Defect_Rate_% on Y-axis, each point labeled by Design_ID.

Plot Test_Coverage_% vs Defect_Rate_% with labels.

Expected Result

Scatter plot shows inverse relationship between test coverage and defect rate.

7

Step 7: Add filters to the dashboard to select designs by Boundary_Scan usage and Low_Test_Coverage flag.

Add slicers for Boundary_Scan (Yes/No) and Low_Test_Coverage (Yes/No).

Expected Result

User can filter dashboard to focus on designs missing boundary scan or with low coverage.

8

Step 8: Review dashboard and highlight designs needing improvement in DFT to reduce defects.

Use visual cues and table flags to identify PCB002, PCB004, PCB006, PCB008 as priority.

Expected Result

Dashboard clearly identifies designs with poor DFT metrics and high defects.

Final Result

Bar chart: Test Coverage % per Design_ID with red bars for <70%

↓

Scatter plot: Test Coverage % vs Defect Rate % showing inverse trend

✓Designs without boundary scan and with low test coverage have higher defect rates.

✓PCB002, PCB004, PCB006, and PCB008 need improved DFT to reduce defects.

✓Higher test coverage correlates with lower defect rates in PCB designs.

Bonus Challenge

Add a calculated measure to estimate potential defect reduction if low coverage designs improve test coverage to 80%.

Show Hint

Create a measure that calculates the difference in defect rate assuming test coverage increases to 80%, then sum potential defect reduction.

Practice

1. What is the main purpose of Design for Testability (DFT) in PCB design?

easy

A. To make PCBs easier to test and fix

B. To reduce the size of the PCB

C. To improve the color of the PCB

D. To increase the power consumption

Solution

1. Step 1: Understand the goal of DFT

   DFT is focused on making printed circuit boards easier to test and repair.

2. Step 2: Compare options to DFT purpose

   Only To make PCBs easier to test and fix matches this goal; others relate to unrelated PCB aspects.

3. Final Answer:

   To make PCBs easier to test and fix -> Option A

4. Quick Check:

   DFT purpose = easier testing and fixing [OK]

Hint: DFT helps find and fix PCB problems easily [OK]

Common Mistakes:

• Confusing DFT with PCB size reduction
• Thinking DFT changes PCB color
• Assuming DFT increases power use

2. Which of the following is a common method used in DFT for PCBs?

easy

A. Solder mask color

B. Scan chains

C. Thermal vias

D. Silkscreen printing

Solution

1. Step 1: Identify DFT methods

   Common DFT methods include scan chains, test points, and boundary scan.

2. Step 2: Match options to DFT methods

   Only scan chains are a DFT method; others relate to PCB manufacturing or appearance.

3. Final Answer:

   Scan chains -> Option B

4. Quick Check:

   Scan chains = DFT method [OK]

Hint: Scan chains help test internal PCB logic easily [OK]

Common Mistakes:

• Choosing solder mask color as a test method
• Confusing thermal vias with test points
• Thinking silkscreen printing is for testing

3. Consider a PCB design with scan chains implemented. What is the expected benefit when running tests?

medium

A. Faster detection of faults inside the PCB logic

B. Reduced power consumption during operation

C. Improved signal speed on all traces

D. Automatic repair of faulty components

Solution

1. Step 1: Understand scan chains role

   Scan chains allow shifting test data through internal logic to detect faults quickly.

2. Step 2: Evaluate options against scan chain benefits

   Only faster fault detection matches scan chain purpose; others are unrelated or incorrect.

3. Final Answer:

   Faster detection of faults inside the PCB logic -> Option A

4. Quick Check:

   Scan chains = faster fault detection [OK]

Hint: Scan chains speed up finding PCB logic faults [OK]

Common Mistakes:

• Assuming scan chains reduce power use
• Thinking scan chains improve signal speed
• Believing scan chains fix faults automatically

4. A PCB design includes test points but the test engineer reports difficulty accessing them during testing. What is the likely error in the DFT implementation?

medium

A. Test points too large and causing shorts

B. Test points connected to power lines only

C. Test points made of non-conductive material

D. Test points placed under components or inaccessible areas

Solution

1. Step 1: Analyze test point accessibility issue

   If test points are hard to access, they may be physically blocked or poorly placed.

2. Step 2: Match options to accessibility problem

   Only Test points placed under components or inaccessible areas explains physical inaccessibility; others describe electrical or material issues.

3. Final Answer:

   Test points placed under components or inaccessible areas -> Option D

4. Quick Check:

   Inaccessible test points = poor placement [OK]

Hint: Place test points where probes can easily reach [OK]

Common Mistakes:

• Confusing electrical connection issues with physical access
• Thinking test points can be non-conductive
• Assuming large test points cause shorts

5. You are designing a complex PCB and want to ensure efficient testing after manufacturing. Which combination of DFT techniques should you plan early to minimize test time and cost?

hard

A. Add extra layers and increase trace width

B. Use only visual inspection and manual probing

C. Use boundary scan and test points placed for easy access

D. Place test points randomly and rely on functional testing

Solution

1. Step 1: Identify effective DFT techniques for complex PCBs

   Boundary scan and well-placed test points enable automated and fast testing.

2. Step 2: Evaluate options for minimizing test time and cost

   Use boundary scan and test points placed for easy access combines proven DFT methods; others increase cost or reduce test efficiency.

3. Final Answer:

   Use boundary scan and test points placed for easy access -> Option C

4. Quick Check:

   Boundary scan + good test points = efficient testing [OK]

Hint: Plan boundary scan and test points early for easy testing [OK]

Common Mistakes:

• Thinking extra layers reduce test time
• Relying only on visual/manual testing
• Placing test points without planning