Design for testability (DFT) in PCB Design - Dashboard Guide

Dashboard Mode - Design for testability (DFT)

Business Question

How can we monitor and improve the test coverage and fault detection efficiency in our PCB designs using Design for Testability (DFT) metrics?

Sample Data: PCB Test Metrics

PCB_ID	Test_Points	Tested_Points	Faults_Detected	Total_Faults	Test_Time_Minutes
PCB001	100	95	5	6	30
PCB002	120	110	8	10	40
PCB003	90	85	4	5	25
PCB004	150	140	12	15	50
PCB005	80	75	3	4	20

Dashboard Components

• KPI Card: Average Test Coverage (%)
  Formula: Average Test Coverage = AVERAGE(Tested_Points / Test_Points * 100)
  Result: ((95/100)*100 + (110/120)*100 + (85/90)*100 + (140/150)*100 + (75/80)*100) / 5 = 93.44%
• KPI Card: Average Fault Detection Rate (%)
  Formula: Average Fault Detection Rate = AVERAGE(Faults_Detected / Total_Faults * 100)
  Result: ((5/6)*100 + (8/10)*100 + (4/5)*100 + (12/15)*100 + (3/4)*100) / 5 = 79.67%
• KPI Card: Average Test Time (Minutes)
  Formula: Average Test Time = AVERAGE(Test_Time_Minutes)
  Result: (30 + 40 + 25 + 50 + 20) / 5 = 33 minutes
• Bar Chart: Test Coverage per PCB
  X-axis: PCB_ID
  Y-axis: Test Coverage (%) = Tested_Points / Test_Points * 100
  Values:
  PCB001: 95%
  PCB002: 91.67%
  PCB003: 94.44%
  PCB004: 93.33%
  PCB005: 93.75%
• Bar Chart: Fault Detection Rate per PCB
  X-axis: PCB_ID
  Y-axis: Fault Detection Rate (%) = Faults_Detected / Total_Faults * 100
  Values:
  PCB001: 83.33%
  PCB002: 80%
  PCB003: 80%
  PCB004: 80%
  PCB005: 75%
• Table: Detailed PCB Test Data
  Columns: PCB_ID, Test_Points, Tested_Points, Faults_Detected, Total_Faults, Test_Time_Minutes

Dashboard Layout

+--------------------------------------------------+
| Average Test Coverage (%) | Average Fault Detection Rate (%) | Average Test Time (min) |
+--------------------------+--------------------------------+-------------------------+
|                      Bar Chart: Test Coverage per PCB                      |
+--------------------------------------------------------------------------+
|                    Bar Chart: Fault Detection Rate per PCB                |
+--------------------------------------------------------------------------+
|                            Table: Detailed PCB Test Data                  |
+--------------------------------------------------------------------------+

Interactivity

A filter slicer for PCB_ID allows selecting one or multiple PCBs. When a PCB_ID is selected:

• All KPI cards update to show averages only for the selected PCBs.
• Both bar charts update to display data only for the selected PCBs.
• The detailed table filters to show only the selected PCB rows.

This helps focus on specific PCB designs to analyze their testability performance.

Self Check

If you add a filter to select only PCB002 and PCB004, which components update and what are the new average test coverage and fault detection rate?

• All KPI cards update to averages for PCB002 and PCB004 only.
• Bar charts show only these two PCBs.
• Table shows only rows for PCB002 and PCB004.

Calculations:

• Test Coverage: ((110/120)*100 + (140/150)*100) / 2 = (91.67 + 93.33) / 2 = 92.5%
• Fault Detection Rate: ((8/10)*100 + (12/15)*100) / 2 = (80 + 80) / 2 = 80%

Key Result

Dashboard shows PCB test coverage, fault detection rates, and test times to monitor Design for Testability effectiveness.

Practice

1. What is the main purpose of Design for Testability (DFT) in PCB design?

easy

A. To make PCBs easier to test and fix

B. To reduce the size of the PCB

C. To improve the color of the PCB

D. To increase the power consumption

Solution

1. Step 1: Understand the goal of DFT

   DFT is focused on making printed circuit boards easier to test and repair.

2. Step 2: Compare options to DFT purpose

   Only To make PCBs easier to test and fix matches this goal; others relate to unrelated PCB aspects.

3. Final Answer:

   To make PCBs easier to test and fix -> Option A

4. Quick Check:

   DFT purpose = easier testing and fixing [OK]

Hint: DFT helps find and fix PCB problems easily [OK]

Common Mistakes:

• Confusing DFT with PCB size reduction
• Thinking DFT changes PCB color
• Assuming DFT increases power use

2. Which of the following is a common method used in DFT for PCBs?

easy

A. Solder mask color

B. Scan chains

C. Thermal vias

D. Silkscreen printing

Solution

1. Step 1: Identify DFT methods

   Common DFT methods include scan chains, test points, and boundary scan.

2. Step 2: Match options to DFT methods

   Only scan chains are a DFT method; others relate to PCB manufacturing or appearance.

3. Final Answer:

   Scan chains -> Option B

4. Quick Check:

   Scan chains = DFT method [OK]

Hint: Scan chains help test internal PCB logic easily [OK]

Common Mistakes:

• Choosing solder mask color as a test method
• Confusing thermal vias with test points
• Thinking silkscreen printing is for testing

3. Consider a PCB design with scan chains implemented. What is the expected benefit when running tests?

medium

A. Faster detection of faults inside the PCB logic

B. Reduced power consumption during operation

C. Improved signal speed on all traces

D. Automatic repair of faulty components

Solution

1. Step 1: Understand scan chains role

   Scan chains allow shifting test data through internal logic to detect faults quickly.

2. Step 2: Evaluate options against scan chain benefits

   Only faster fault detection matches scan chain purpose; others are unrelated or incorrect.

3. Final Answer:

   Faster detection of faults inside the PCB logic -> Option A

4. Quick Check:

   Scan chains = faster fault detection [OK]

Hint: Scan chains speed up finding PCB logic faults [OK]

Common Mistakes:

• Assuming scan chains reduce power use
• Thinking scan chains improve signal speed
• Believing scan chains fix faults automatically

4. A PCB design includes test points but the test engineer reports difficulty accessing them during testing. What is the likely error in the DFT implementation?

medium

A. Test points too large and causing shorts

B. Test points connected to power lines only

C. Test points made of non-conductive material

D. Test points placed under components or inaccessible areas

Solution

1. Step 1: Analyze test point accessibility issue

   If test points are hard to access, they may be physically blocked or poorly placed.

2. Step 2: Match options to accessibility problem

   Only Test points placed under components or inaccessible areas explains physical inaccessibility; others describe electrical or material issues.

3. Final Answer:

   Test points placed under components or inaccessible areas -> Option D

4. Quick Check:

   Inaccessible test points = poor placement [OK]

Hint: Place test points where probes can easily reach [OK]

Common Mistakes:

• Confusing electrical connection issues with physical access
• Thinking test points can be non-conductive
• Assuming large test points cause shorts

5. You are designing a complex PCB and want to ensure efficient testing after manufacturing. Which combination of DFT techniques should you plan early to minimize test time and cost?

hard

A. Add extra layers and increase trace width

B. Use only visual inspection and manual probing

C. Use boundary scan and test points placed for easy access

D. Place test points randomly and rely on functional testing

Solution

1. Step 1: Identify effective DFT techniques for complex PCBs

   Boundary scan and well-placed test points enable automated and fast testing.

2. Step 2: Evaluate options for minimizing test time and cost

   Use boundary scan and test points placed for easy access combines proven DFT methods; others increase cost or reduce test efficiency.

3. Final Answer:

   Use boundary scan and test points placed for easy access -> Option C

4. Quick Check:

   Boundary scan + good test points = efficient testing [OK]

Hint: Plan boundary scan and test points early for easy testing [OK]

Common Mistakes:

• Thinking extra layers reduce test time
• Relying only on visual/manual testing
• Placing test points without planning