Why DMA with UART for bulk transfer in Embedded C? - Purpose & Use Cases

The Big Idea

What if your CPU could relax while data moves itself perfectly in the background?

The Scenario

Imagine you need to send or receive a large file over a serial connection using UART. Doing this byte by byte with the CPU manually reading and writing each byte feels like filling a bucket with a teaspoon--slow and tiring.

The Problem

Manually handling each byte wastes CPU time, making your program slow and unresponsive. It's easy to miss bytes or cause delays, especially when the CPU has other tasks to do. This leads to errors and poor performance.

The Solution

DMA (Direct Memory Access) lets the hardware move big chunks of data between memory and UART automatically. This frees the CPU to do other things while data flows smoothly and quickly in the background.

Before vs After

✗ Before

while(!uart_tx_ready()) {}
uart_send_byte(data[i]);

✓ After

dma_start_transfer(uart_tx_buffer, data, length);

What It Enables

DMA with UART enables fast, efficient bulk data transfer without burdening the CPU, making embedded systems more responsive and reliable.

Real Life Example

Think of a GPS device sending continuous location data to a display. Using DMA with UART, the GPS can send large data streams smoothly while the CPU handles navigation calculations.

Key Takeaways

Manual UART byte handling is slow and error-prone.

DMA automates bulk data transfer, freeing CPU resources.

This leads to faster, more reliable communication in embedded systems.

Practice

1. What is the main advantage of using DMA with UART for bulk data transfer?

easy

A. It reduces CPU load by handling data transfer automatically.

B. It increases the UART baud rate beyond hardware limits.

C. It encrypts data during transmission for security.

D. It allows UART to work without any clock signal.

Solution

1. Step 1: Understand DMA role in UART transfer

   DMA transfers data directly between memory and UART without CPU intervention for each byte.

2. Step 2: Identify the benefit of reduced CPU load

   This frees CPU to perform other tasks while data moves in background.

3. Final Answer:

   It reduces CPU load by handling data transfer automatically. -> Option A

4. Quick Check:

   DMA offloads CPU [OK]

Hint: DMA moves data without CPU, so CPU load drops [OK]

Common Mistakes:

• Thinking DMA increases UART speed beyond hardware limits
• Confusing DMA with encryption or clock control
• Assuming UART can work without clock signal

2. Which of the following code snippets correctly enables UART DMA transmission in embedded C?

easy

A. UART->CR3 |= USART_CR3_DMAT;

B. UART->CR1 |= USART_CR1_DMAT;

C. DMA->CR |= DMA_CR_EN;

D. UART->BRR = USART_BRR_DMAT;

Solution

1. Step 1: Identify UART register for DMA transmit enable

   UART control register 3 (CR3) contains the DMAT bit to enable DMA for transmission.

2. Step 2: Check correct bit and register usage

   Setting USART_CR3_DMAT in UART->CR3 enables DMA transmit requests.

3. Final Answer:

   UART->CR3 |= USART_CR3_DMAT; -> Option A

4. Quick Check:

   DMA transmit enable bit is in CR3 [OK]

Hint: DMA transmit enable is in UART CR3 register [OK]

Common Mistakes:

• Using CR1 instead of CR3 for DMA transmit enable
• Confusing DMA channel enable with UART DMA request enable
• Setting baud rate register instead of control bits

3. Given this DMA setup code for UART RX bulk transfer, what will be the value of DMA->NDTR after starting the transfer?

DMA->CCR = DMA_CCR_MINC | DMA_CCR_TCIE;
DMA->CNDTR = 100;
DMA->CPAR = (uint32_t)&UART->RDR;
DMA->CMAR = (uint32_t)rx_buffer;
DMA->CCR |= DMA_CCR_EN;

medium

A. 0

B. 99

C. 100

D. Undefined

Solution

1. Step 1: Understand DMA CNDTR register role

   CNDTR holds the number of data items to transfer; initially set to 100.

2. Step 2: Check when CNDTR changes

   CNDTR decrements only after each data transfer, so right after enabling DMA, it remains 100.

3. Final Answer:

   100 -> Option C

4. Quick Check:

   DMA transfer count starts at set value = 100 [OK]

Hint: DMA count decrements after transfer, not immediately [OK]

Common Mistakes:

• Assuming CNDTR decrements immediately on enable
• Confusing CNDTR with current data register
• Thinking CNDTR resets to zero on start

4. Identify the error in this DMA UART transmit setup code snippet:

DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;
DMA->CNDTR = 50;
DMA->CPAR = (uint32_t)&UART->TDR;
DMA->CMAR = (uint32_t)tx_buffer;
DMA->CCR |= DMA_CCR_EN;
UART->CR3 &= ~USART_CR3_DMAT;

medium

A. DMA direction bit is set incorrectly for UART transmit.

B. UART DMA transmit request is disabled after enabling DMA.

C. Memory increment mode is not enabled.

D. Peripheral address points to wrong UART register.

Solution

1. Step 1: Check UART DMA transmit enable bit

   UART->CR3 must have DMAT bit set to enable DMA requests for transmit.

2. Step 2: Identify disabling of DMAT bit

   Code clears DMAT bit after DMA enable, disabling UART DMA transmit requests, so transfer won't start.

3. Final Answer:

   UART DMA transmit request is disabled after enabling DMA. -> Option B

4. Quick Check:

   DMAT bit must be set for DMA transmit [OK]

Hint: Keep UART DMAT bit set to allow DMA transmit [OK]

Common Mistakes:

• Disabling UART DMA transmit request after DMA enable
• Confusing DMA direction bit meaning
• Forgetting to enable memory increment mode

5. You want to transfer 256 bytes from a memory buffer to UART using DMA. Which sequence correctly sets up the DMA and UART for this bulk transfer?

hard

A. Set DMA source to UART RDR, destination to buffer, length 256; enable UART DMAR bit; enable DMA channel.

B. Set DMA source to UART TDR, destination to buffer, length 256; enable UART DMAR bit; enable DMA channel.

C. Set DMA source to buffer, destination to UART RDR, length 256; enable UART DMAT bit; enable DMA channel.

D. Set DMA source to buffer, destination to UART TDR, length 256; enable UART DMAT bit; enable DMA channel.

Solution

1. Step 1: Identify direction for UART transmit DMA

   For UART transmit, DMA source is memory buffer, destination is UART TDR register.

2. Step 2: Enable UART DMA transmit request and DMA channel

   Set UART DMAT bit to enable DMA requests on transmit, then enable DMA channel to start transfer.

3. Final Answer:

   Set DMA source to buffer, destination to UART TDR, length 256; enable UART DMAT bit; enable DMA channel. -> Option D

4. Quick Check:

   Memory to UART TDR + DMAT enabled [OK]

Hint: For UART TX DMA: memory source, UART TDR destination, enable DMAT [OK]

Common Mistakes:

• Confusing UART TDR and RDR registers for source/destination
• Using DMAR bit for transmit instead of DMAT
• Setting DMA direction opposite to data flow