DMA with UART for bulk transfer in Embedded C - Step-by-Step Execution

Concept Flow - DMA with UART for bulk transfer

Start UART DMA Transfer

↓

Configure DMA with buffer

↓

Enable UART DMA Request

↓

DMA Transfers Data Automatically

↓

DMA Transfer Complete Interrupt

↓

Process Received Data

↓

End

The flow shows how DMA is set up to transfer data from UART automatically, triggering an interrupt when done.

Execution Sample

Embedded C

void start_uart_dma(void) {
  DMA_Config(UART_DR, buffer, size);
  UART_EnableDMA();
  DMA_Start();
}

void DMA_IRQHandler(void) {
  if (DMA_TransferComplete()) {
    process_data(buffer);
  }
}

This code configures DMA to transfer data from UART to a buffer and processes data when transfer completes.

Execution Table

Step	Action	DMA State	UART State	Buffer Content	Interrupt
1	Configure DMA with buffer and size	Configured	Idle	Empty	No
2	Enable UART DMA request	Configured	Ready for DMA	Empty	No
3	Start DMA transfer	Running	Receiving Data	Filling...	No
4	DMA transfers bytes automatically	Running	Receiving Data	Partial Data	No
5	DMA transfer completes full size	Complete	Idle	Full Data	Yes
6	DMA interrupt triggers	Complete	Idle	Full Data	Yes
7	Process received data in buffer	Idle	Idle	Processed Data	No
8	End of transfer cycle	Idle	Idle	Processed Data	No

💡 DMA transfer completes full size, triggers interrupt, then data is processed.

Variable Tracker

Variable	Start	After Step 3	After Step 5	After Step 7	Final
DMA State	Not Configured	Running	Complete	Idle	Idle
UART State	Idle	Receiving Data	Idle	Idle	Idle
Buffer Content	Empty	Filling...	Full Data	Processed Data	Processed Data
Interrupt	No	No	Yes	No	No

Key Moments - 3 Insights

Why does the DMA transfer happen without CPU intervention?

Because DMA is configured to move data directly from UART to buffer automatically (see execution_table steps 3-5).

When does the CPU get notified that data transfer is complete?

CPU is notified by the DMA transfer complete interrupt at step 6 in the execution_table.

What happens to the buffer content after DMA transfer completes?

Buffer contains full data and then is processed by CPU as shown in steps 5 to 7.

Visual Quiz - 3 Questions

Look at the execution_table, what is the DMA State at step 4?

A Configured

B Complete

C Running

D Idle

💡 Hint

Check the DMA State column at step 4 in the execution_table.

At which step does the DMA interrupt trigger?

A Step 5

B Step 6

C Step 3

D Step 7

💡 Hint

Look for the Interrupt column showing 'Yes' in the execution_table.

If the buffer size was smaller, how would the Buffer Content at step 5 change?

A It would have partial data

B It would be empty

C It would have full data as before

D It would cause an error

💡 Hint

Refer to Buffer Content changes in variable_tracker and execution_table steps 4 and 5.

Concept Snapshot

DMA with UART bulk transfer:
- Configure DMA with buffer and size
- Enable UART DMA request
- Start DMA transfer (automatic data move)
- DMA triggers interrupt on completion
- CPU processes data from buffer
- Reduces CPU load during data reception

Full Transcript

This visual execution trace shows how DMA works with UART for bulk data transfer. First, DMA is configured with a buffer and size. Then UART DMA request is enabled. When DMA starts, it automatically transfers data from UART to the buffer without CPU intervention. Once the full data size is transferred, DMA triggers an interrupt to notify the CPU. The CPU then processes the received data in the buffer. This method reduces CPU load and allows efficient data reception.

Practice

1. What is the main advantage of using DMA with UART for bulk data transfer?

easy

A. It reduces CPU load by handling data transfer automatically.

B. It increases the UART baud rate beyond hardware limits.

C. It encrypts data during transmission for security.

D. It allows UART to work without any clock signal.

Solution

1. Step 1: Understand DMA role in UART transfer

   DMA transfers data directly between memory and UART without CPU intervention for each byte.

2. Step 2: Identify the benefit of reduced CPU load

   This frees CPU to perform other tasks while data moves in background.

3. Final Answer:

   It reduces CPU load by handling data transfer automatically. -> Option A

4. Quick Check:

   DMA offloads CPU [OK]

Hint: DMA moves data without CPU, so CPU load drops [OK]

Common Mistakes:

• Thinking DMA increases UART speed beyond hardware limits
• Confusing DMA with encryption or clock control
• Assuming UART can work without clock signal

2. Which of the following code snippets correctly enables UART DMA transmission in embedded C?

easy

A. UART->CR3 |= USART_CR3_DMAT;

B. UART->CR1 |= USART_CR1_DMAT;

C. DMA->CR |= DMA_CR_EN;

D. UART->BRR = USART_BRR_DMAT;

Solution

1. Step 1: Identify UART register for DMA transmit enable

   UART control register 3 (CR3) contains the DMAT bit to enable DMA for transmission.

2. Step 2: Check correct bit and register usage

   Setting USART_CR3_DMAT in UART->CR3 enables DMA transmit requests.

3. Final Answer:

   UART->CR3 |= USART_CR3_DMAT; -> Option A

4. Quick Check:

   DMA transmit enable bit is in CR3 [OK]

Hint: DMA transmit enable is in UART CR3 register [OK]

Common Mistakes:

• Using CR1 instead of CR3 for DMA transmit enable
• Confusing DMA channel enable with UART DMA request enable
• Setting baud rate register instead of control bits

3. Given this DMA setup code for UART RX bulk transfer, what will be the value of DMA->NDTR after starting the transfer?

DMA->CCR = DMA_CCR_MINC | DMA_CCR_TCIE;
DMA->CNDTR = 100;
DMA->CPAR = (uint32_t)&UART->RDR;
DMA->CMAR = (uint32_t)rx_buffer;
DMA->CCR |= DMA_CCR_EN;

medium

A. 0

B. 99

C. 100

D. Undefined

Solution

1. Step 1: Understand DMA CNDTR register role

   CNDTR holds the number of data items to transfer; initially set to 100.

2. Step 2: Check when CNDTR changes

   CNDTR decrements only after each data transfer, so right after enabling DMA, it remains 100.

3. Final Answer:

   100 -> Option C

4. Quick Check:

   DMA transfer count starts at set value = 100 [OK]

Hint: DMA count decrements after transfer, not immediately [OK]

Common Mistakes:

• Assuming CNDTR decrements immediately on enable
• Confusing CNDTR with current data register
• Thinking CNDTR resets to zero on start

4. Identify the error in this DMA UART transmit setup code snippet:

DMA->CCR = DMA_CCR_MINC | DMA_CCR_DIR;
DMA->CNDTR = 50;
DMA->CPAR = (uint32_t)&UART->TDR;
DMA->CMAR = (uint32_t)tx_buffer;
DMA->CCR |= DMA_CCR_EN;
UART->CR3 &= ~USART_CR3_DMAT;

medium

A. DMA direction bit is set incorrectly for UART transmit.

B. UART DMA transmit request is disabled after enabling DMA.

C. Memory increment mode is not enabled.

D. Peripheral address points to wrong UART register.

Solution

1. Step 1: Check UART DMA transmit enable bit

   UART->CR3 must have DMAT bit set to enable DMA requests for transmit.

2. Step 2: Identify disabling of DMAT bit

   Code clears DMAT bit after DMA enable, disabling UART DMA transmit requests, so transfer won't start.

3. Final Answer:

   UART DMA transmit request is disabled after enabling DMA. -> Option B

4. Quick Check:

   DMAT bit must be set for DMA transmit [OK]

Hint: Keep UART DMAT bit set to allow DMA transmit [OK]

Common Mistakes:

• Disabling UART DMA transmit request after DMA enable
• Confusing DMA direction bit meaning
• Forgetting to enable memory increment mode

5. You want to transfer 256 bytes from a memory buffer to UART using DMA. Which sequence correctly sets up the DMA and UART for this bulk transfer?

hard

A. Set DMA source to UART RDR, destination to buffer, length 256; enable UART DMAR bit; enable DMA channel.

B. Set DMA source to UART TDR, destination to buffer, length 256; enable UART DMAR bit; enable DMA channel.

C. Set DMA source to buffer, destination to UART RDR, length 256; enable UART DMAT bit; enable DMA channel.

D. Set DMA source to buffer, destination to UART TDR, length 256; enable UART DMAT bit; enable DMA channel.

Solution

1. Step 1: Identify direction for UART transmit DMA

   For UART transmit, DMA source is memory buffer, destination is UART TDR register.

2. Step 2: Enable UART DMA transmit request and DMA channel

   Set UART DMAT bit to enable DMA requests on transmit, then enable DMA channel to start transfer.

3. Final Answer:

   Set DMA source to buffer, destination to UART TDR, length 256; enable UART DMAT bit; enable DMA channel. -> Option D

4. Quick Check:

   Memory to UART TDR + DMAT enabled [OK]

Hint: For UART TX DMA: memory source, UART TDR destination, enable DMAT [OK]

Common Mistakes:

• Confusing UART TDR and RDR registers for source/destination
• Using DMAR bit for transmit instead of DMAT
• Setting DMA direction opposite to data flow