Timer prescaler and clock division in Embedded C - Step-by-Step Execution

Concept Flow - Timer prescaler and clock division

Start Timer

↓

Input Clock Frequency

↓

Apply Prescaler

↓

Divide Clock Frequency

↓

Timer Counts at New Frequency

↓

Timer Overflow or Compare Event

↓

Interrupt or Action Triggered

The timer starts with an input clock frequency, applies a prescaler to slow it down, then the timer counts at this divided frequency until an event triggers.

Execution Sample

Embedded C

uint32_t timer_freq = 16000000;
uint16_t prescaler = 8;
uint32_t timer_tick = timer_freq / prescaler;
// Timer counts at timer_tick frequency

Calculate timer tick frequency by dividing the input clock by the prescaler.

Execution Table

Step	Variable	Value	Action	Result
1	timer_freq	16000000	Set input clock frequency	16 MHz
2	prescaler	8	Set prescaler value	Divide clock by 8
3	timer_tick	timer_freq / prescaler	Calculate timer tick frequency	2000000 Hz
4	Timer Counting	At 2 MHz	Timer increments counter at this rate	Counts every 0.5 microseconds
5	Timer Overflow	When counter reaches max	Timer triggers event	Interrupt or flag set
6	-	-	Stop	Timer runs until stopped or reset

💡 Timer runs continuously until stopped or overflow event triggers

Variable Tracker

Variable	Start	After Step 2	After Step 3	Final
timer_freq	undefined	16000000	16000000	16000000
prescaler	undefined	8	8	8
timer_tick	undefined	undefined	2000000	2000000

Key Moments - 3 Insights

Why does the timer frequency decrease after applying the prescaler?

Because the prescaler divides the input clock frequency, slowing down the timer increments as shown in step 3 of the execution_table.

What happens if the prescaler is set to 1?

The timer frequency equals the input clock frequency, so the timer counts at the fastest rate possible, as implied in step 3 where prescaler divides the clock.

How does the timer know when to trigger an event?

When the timer counter reaches its maximum value (overflow), it triggers an event as shown in step 5 of the execution_table.

Visual Quiz - 3 Questions

Look at the execution_table, what is the timer_tick frequency after applying the prescaler?

A 16,000,000 Hz

B 8,000,000 Hz

C 2,000,000 Hz

D 125,000 Hz

💡 Hint

Check step 3 in the execution_table where timer_tick is calculated.

At which step does the timer trigger an event due to overflow?

A Step 5

B Step 4

C Step 2

D Step 6

💡 Hint

Look for the step mentioning timer overflow and event trigger in the execution_table.

If the prescaler is changed from 8 to 4, how does timer_tick change?

A It halves

B It doubles

C It stays the same

D It becomes zero

💡 Hint

Refer to variable_tracker and step 3 in execution_table to see how prescaler affects timer_tick.

Concept Snapshot

Timer prescaler divides the input clock frequency.
Timer frequency = Input clock / Prescaler.
Lower timer frequency means slower counting.
Timer counts until overflow triggers event.
Prescaler controls timer speed easily.

Full Transcript

This visual execution shows how a timer uses a prescaler to divide its input clock frequency. Starting with a 16 MHz clock, applying a prescaler of 8 divides the frequency to 2 MHz. The timer then counts at this slower rate, incrementing every 0.5 microseconds. When the timer counter reaches its maximum value, it triggers an overflow event, which can generate an interrupt or set a flag. Changing the prescaler changes the timer tick frequency inversely. This helps control how fast the timer counts without changing the main clock.

Practice

1. What is the main purpose of a timer prescaler in embedded C programming?

easy

A. To generate an interrupt on every clock cycle

B. To increase the CPU clock speed

C. To divide the main clock frequency and slow down the timer counting

D. To reset the timer counter automatically

Solution

1. Step 1: Understand the role of a prescaler

   A prescaler divides the main clock frequency to slow down the timer's counting speed.

2. Step 2: Compare options with prescaler function

   Only To divide the main clock frequency and slow down the timer counting correctly describes this function; others describe unrelated timer features.

3. Final Answer:

   To divide the main clock frequency and slow down the timer counting -> Option C

4. Quick Check:

   Prescaler divides clock = To slow timer [OK]

Hint: Prescaler always divides clock to slow timer [OK]

Common Mistakes:

• Confusing prescaler with timer reset
• Thinking prescaler speeds up the clock
• Assuming prescaler triggers interrupts

2. Which of the following is the correct way to set a prescaler value of 8 for a timer in embedded C?

easy

A. TCCR0 |= (1 << CS01);

B. TCCR0 |= (1 << CS00);

C. TCCR0 |= (1 << CS02);

D. TCCR0 |= (1 << CS01) | (1 << CS00);

Solution

1. Step 1: Recall prescaler bits for timer0

   For prescaler 8, only bit CS01 must be set.

2. Step 2: Match bits to options

   TCCR0 |= (1 << CS01); sets CS01 bit, correctly configuring prescaler 8.

3. Final Answer:

   TCCR0 |= (1 << CS01); -> Option A

4. Quick Check:

   Prescaler 8 = CS01 set only [OK]

Hint: Check datasheet bits for prescaler values [OK]

Common Mistakes:

• Setting multiple bits for prescaler 8
• Confusing bit positions for prescaler values
• Using wrong register for timer control

3. Given a microcontroller clock of 16 MHz and a timer prescaler set to 64, what is the timer tick frequency?

medium

A. 1,000,000 Hz

B. 250,000 Hz

C. 16,000,000 Hz

D. 64 Hz

Solution

1. Step 1: Calculate timer tick frequency

   Timer tick frequency = CPU clock / prescaler = 16,000,000 / 64 = 250,000 Hz.

2. Step 2: Compare with options

   250,000 Hz matches the calculated frequency exactly.

3. Final Answer:

   250,000 Hz -> Option B

4. Quick Check:

   16MHz/64 = 250kHz [OK]

Hint: Divide clock by prescaler for tick frequency [OK]

Common Mistakes:

• Multiplying instead of dividing clock by prescaler
• Using wrong prescaler value
• Confusing frequency units

4. Identify the error in this code snippet setting a prescaler of 256 for Timer1:

  TCCR1B = (1 << CS12) | (1 << CS10);

medium

A. CS12 bit is missing

B. No error, code is correct

C. TCCR1B register is incorrect for prescaler

D. CS10 should not be set for prescaler 256

Solution

1. Step 1: Check prescaler bits for 256 on Timer1

   Prescaler 256 requires only CS12 bit set; CS10 must be cleared.

2. Step 2: Analyze given code

   Code sets both CS12 and CS10 bits, which corresponds to prescaler 1024, not 256.

3. Final Answer:

   CS10 should not be set for prescaler 256 -> Option D

4. Quick Check:

   Prescaler 256 = only CS12 set [OK]

Hint: Only set bits matching prescaler exactly [OK]

Common Mistakes:

• Setting extra bits causing wrong prescaler
• Confusing prescaler bit combinations
• Assuming code is correct without checking datasheet

5. You want to measure a 1-second delay using a 16-bit timer with a 16 MHz clock. Which prescaler value should you choose to make the timer count up to 1 second without overflow? (Timer max count = 65535)

hard

A. Prescaler 1024

B. Prescaler 64

C. Prescaler 128

D. Prescaler 8

Solution

1. Step 1: Calculate timer tick frequency for each prescaler

   Tick frequency = 16,000,000 / prescaler. For 1024: 16,000,000 / 1024 ≈ 15,625 Hz.

2. Step 2: Calculate max timer duration

   Max duration = max count / tick frequency = 65535 / 15,625 ≈ 4.19 seconds, which covers 1 second.

3. Step 3: Check smaller prescalers

   Prescaler 128 gives 125,000 ticks per second, 64 gives 250,000, and 8 gives 2,000,000--all exceeding 65,535, causing overflow before 1 second.

4. Final Answer:

   Prescaler 1024 -> Option A

5. Quick Check:

   Prescaler 1024 allows 1s count without overflow [OK]

Hint: Choose prescaler so max count ≥ ticks in 1 second [OK]

Common Mistakes:

• Ignoring timer max count limit
• Choosing prescaler too small causing overflow
• Not calculating ticks per second correctly