SPI master-slave architecture in Embedded C - Step-by-Step Execution

Concept Flow - SPI master-slave architecture

Master initiates communication

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Master sends clock pulses

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Master sends data bits

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Slave reads data bits on clock edges

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Slave sends data bits back (optional)

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Master reads slave data bits

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Communication ends when master stops clock

The SPI master controls the clock and data flow, sending bits to the slave while the slave reads and optionally sends data back, synchronized by the clock.

Execution Sample

Embedded C

void SPI_Master_Transmit(uint8_t data) {
    for (int i = 7; i >= 0; i--) {
        // Set MOSI according to data bit
        // Toggle clock
        // Read MISO if needed
    }
}

This code sends 8 bits from master to slave, one bit at a time, toggling the clock each time.

Execution Table

Bit Index	Data Bit Sent (MOSI)	Clock State	Slave Reads Bit	Master Reads Bit (MISO)
7	1	Low->High	Reads 1	Reads 0
6	0	Low->High	Reads 0	Reads 1
5	1	Low->High	Reads 1	Reads 0
4	1	Low->High	Reads 1	Reads 1
3	0	Low->High	Reads 0	Reads 0
2	0	Low->High	Reads 0	Reads 1
1	1	Low->High	Reads 1	Reads 0
0	0	Low->High	Reads 0	Reads 1
-	-	-	-	Communication ends after 8 bits

💡 All 8 bits sent and received, master stops clock to end communication

Variable Tracker

Variable	Start	After Bit 7	After Bit 6	After Bit 5	After Bit 4	After Bit 3	After Bit 2	After Bit 1	After Bit 0	Final
MOSI (Master Out Slave In)	N/A	1	0	1	1	0	0	1	0	Last bit sent
Clock	Low	High	High	High	High	High	High	High	High	Stopped
Slave Read Bit	N/A	1	0	1	1	0	0	1	0	All bits read
MISO (Master In Slave Out)	N/A	0	1	0	1	0	1	0	1	All bits read by master

Key Moments - 3 Insights

Why does the master control the clock and not the slave?

The master controls the clock to synchronize data transfer; without the clock, the slave wouldn't know when to read or send bits. See execution_table rows where clock toggles before data read.

How does the slave know which bit is being sent?

The slave reads the MOSI line on the clock's rising edge, so each clock pulse tells the slave to read the next bit. This is shown in execution_table where slave reads bits on clock transitions.

Can the slave send data back at the same time?

Yes, SPI allows full-duplex communication; while master sends bits on MOSI, slave sends bits on MISO simultaneously, as seen in execution_table where master reads MISO each bit.

Visual Quiz - 3 Questions

Look at the execution_table, what is the MOSI bit sent at Bit Index 4?

A 0

B 1

C Does not send at Bit 4

D Same as Bit 7

💡 Hint

Check the 'Data Bit Sent (MOSI)' column at row with Bit Index 4

At which bit index does the master read a '1' from MISO for the first time?

A Bit 7

B Bit 4

C Bit 6

D Bit 0

💡 Hint

Look at 'Master Reads Bit (MISO)' column and find first '1'

If the clock stopped after Bit 2, what would happen?

A Communication ends early, only 6 bits sent

B Slave sends all bits anyway

C Master reads all 8 bits regardless

D Clock stopping has no effect

💡 Hint

Refer to exit_note and understand clock controls data transfer

Concept Snapshot

SPI Master-Slave Architecture:
- Master controls clock and data flow
- Data sent bit-by-bit on MOSI line
- Slave reads bits on clock edges
- Slave can send data back on MISO simultaneously
- Communication ends when master stops clock

Full Transcript

SPI (Serial Peripheral Interface) uses a master-slave setup where the master controls the clock signal. The master sends data bits one by one on the MOSI line, toggling the clock each time. The slave reads these bits on the clock's rising edge. At the same time, the slave can send data back on the MISO line, which the master reads. This process continues for 8 bits or more, and communication ends when the master stops the clock. The master always controls timing to keep both sides in sync.