PWM generation using timers in Embedded C - Step-by-Step Execution

Concept Flow - PWM generation using timers

Configure Timer Prescaler and Period

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Set Timer Mode to PWM

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Set PWM Duty Cycle

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Start Timer

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Timer Counts Up

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Compare Counter with Duty Cycle

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Counter < Duty

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Output HIGH

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Repeat Counting

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PWM Signal

The timer is set up with a prescaler and period, configured for PWM mode, then the duty cycle is set. The timer counts up, and the output pin is set HIGH or LOW depending on the counter compared to the duty cycle, creating a PWM signal.

Execution Sample

Embedded C

TIM_HandleTypeDef htim2;

void PWM_Init() {
  htim2.Init.Prescaler = 79;
  htim2.Init.Period = 999;
  HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
}

void Set_Duty(uint16_t duty) {
  __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, duty);
}

This code initializes a timer for PWM with a prescaler and period, starts PWM on channel 1, and sets the duty cycle by changing the compare value.

Execution Table

Step	Timer Counter (CNT)	Duty Cycle (CCR)	Condition (CNT < CCR)	Output Pin	Action
1	0	500	True	HIGH	Timer starts counting from 0, output HIGH
2	100	500	True	HIGH	Counter less than duty, output stays HIGH
3	499	500	True	HIGH	Counter still less than duty, output HIGH
4	500	500	False	LOW	Counter equals duty, output switches LOW
5	700	500	False	LOW	Counter greater than duty, output LOW
6	999	500	False	LOW	Counter reaches period, output LOW
7	0	500	True	HIGH	Counter resets to 0, output HIGH again
Exit	Counter resets after reaching Period				PWM cycle repeats continuously

💡 Timer counter resets after reaching the period, PWM signal repeats

Variable Tracker

Variable	Start	After Step 1	After Step 4	After Step 7	Final
CNT (Timer Counter)	0	0	500	0	Repeats 0 to 999
CCR (Duty Cycle)	500	500	500	500	Constant at 500
Output Pin	LOW	HIGH	LOW	HIGH	Toggles based on CNT vs CCR

Key Moments - 3 Insights

Why does the output pin go LOW when the counter equals the duty cycle?

Because in the execution_table at step 4, when CNT equals CCR, the condition CNT < CCR becomes false, so the output switches from HIGH to LOW to create the PWM off time.

What happens when the timer counter reaches the period value?

At step 6 and 7 in the execution_table, the counter resets to 0 after reaching the period, restarting the PWM cycle and setting the output HIGH again.

Why is the duty cycle value constant during the PWM cycle?

The duty cycle (CCR) is set once before the timer starts and remains constant during counting, as shown in variable_tracker, controlling how long the output stays HIGH each cycle.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output pin state at step 3 when CNT is 499 and CCR is 500?

A HIGH

B LOW

C Undefined

D Toggling

💡 Hint

Check the 'Output Pin' column at step 3 in the execution_table

At which step does the timer counter reset to 0?

A Step 4

B Step 7

C Step 6

D Step 5

💡 Hint

Look at the 'Timer Counter (CNT)' column and the 'Action' description in the execution_table

If the duty cycle (CCR) is increased to 800, how would the output pin behave between CNT 500 and 700?

A Output switches LOW at CNT 800

B Output switches LOW at CNT 500

C Output stays HIGH

D Output stays LOW

💡 Hint

Refer to the condition CNT < CCR in the execution_table and how output depends on it

Concept Snapshot

PWM generation uses a timer counting from 0 to a set period.
Output pin is HIGH while counter < duty cycle (compare value).
When counter >= duty cycle, output goes LOW.
Timer resets at period, repeating PWM cycle.
Duty cycle controls pulse width (HIGH time).
Prescaler and period set PWM frequency.

Full Transcript

PWM generation using timers works by configuring a timer with a prescaler and period to set the PWM frequency. The timer counts up from zero to the period value repeatedly. A compare register holds the duty cycle value. While the timer counter is less than the duty cycle, the output pin is set HIGH, creating the ON part of the pulse. When the counter reaches or exceeds the duty cycle, the output pin goes LOW, creating the OFF part. This cycle repeats continuously, producing a PWM signal with a pulse width proportional to the duty cycle. The example code initializes the timer, starts PWM, and sets the duty cycle by updating the compare register. The execution table shows the timer counter increasing, output pin switching states based on the counter compared to the duty cycle, and the counter resetting after reaching the period. Key moments clarify why the output changes state and how the timer resets. The visual quiz tests understanding of output states and timer behavior. This method is common in embedded systems to control motors, LEDs, and other devices by varying power with PWM.