Clock polarity and phase (CPOL, CPHA) in Embedded C - Step-by-Step Execution

Concept Flow - Clock polarity and phase (CPOL, CPHA)

Start SPI Clock Cycle

↓

Check CPOL

↓

Check CPHA

↓

Data transfer

↓

End SPI Clock Cycle

This flow shows how CPOL sets clock idle level and CPHA sets when data is sampled during SPI communication.

Execution Sample

Embedded C

/* SPI clock example */
int CPOL = 0; // Clock idle low
int CPHA = 1; // Sample on trailing edge

// Simulate one clock cycle
if (CPOL == 0) {
  // Clock starts low
}
if (CPHA == 1) {
  // Sample data on trailing edge
}

This code simulates SPI clock behavior based on CPOL and CPHA settings.

Execution Table

Step	CPOL	CPHA	Clock Idle Level	Sample Edge	Action
1	0	1	Low	Trailing edge	Start clock cycle with clock low
2	0	1	Low	Trailing edge	Data setup on leading edge (rising)
3	0	1	Low	Trailing edge	Sample data on trailing edge (falling)
4	0	1	Low	Trailing edge	End clock cycle
5	1	0	High	Leading edge	Start clock cycle with clock high
6	1	0	High	Leading edge	Sample data on leading edge (rising)
7	1	0	High	Leading edge	Data setup on trailing edge (falling)
8	1	0	High	Leading edge	End clock cycle

💡 Execution stops after simulating one full clock cycle for each CPOL and CPHA combination.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7	After Step 8
CPOL	0	0	0	0	0	1	1	1	1
CPHA	1	1	1	1	1	0	0	0	0
Clock Level	Undefined	Low	Rising edge	Falling edge	Low	High	Rising edge	Falling edge	High
Sample Edge	Undefined	Trailing	Trailing	Trailing	Trailing	Leading	Leading	Leading	Leading

Key Moments - 3 Insights

Why does CPOL=0 mean the clock idles low?

Because as shown in execution_table step 1, CPOL=0 sets the clock idle level to low before the clock edges start.

When does data sampling happen if CPHA=1?

Data is sampled on the trailing edge of the clock cycle, as seen in execution_table step 3 where sampling occurs on the falling edge.

How do CPOL and CPHA together affect data setup and sampling?

CPOL sets the idle clock level, and CPHA decides if sampling happens on leading or trailing edge, changing when data is stable for reading, as shown by comparing steps 2-3 and 6-7.

Visual Quiz - 3 Questions

Look at the execution_table, what is the clock idle level at step 5?

A High

B Low

C Rising edge

D Falling edge

💡 Hint

Check the 'Clock Idle Level' column at step 5 in the execution_table.

At which step does sampling occur on the trailing edge when CPOL=0 and CPHA=1?

A Step 2

B Step 3

C Step 6

D Step 7

💡 Hint

Look for 'Sample data on trailing edge' in the 'Action' column for CPOL=0 and CPHA=1.

If CPHA changes from 1 to 0 while CPOL=1, when does sampling happen?

A Clock idle

B Trailing edge

C Leading edge

D No sampling

💡 Hint

Refer to steps 5-8 in execution_table where CPOL=1 and CPHA=0.

Concept Snapshot

SPI clock uses CPOL and CPHA to control timing.
CPOL sets clock idle level: 0=low, 1=high.
CPHA sets data sampling edge: 0=leading, 1=trailing.
Together they define when data is stable and sampled.
Correct settings ensure reliable SPI communication.

Full Transcript

This visual execution shows how SPI clock polarity (CPOL) and phase (CPHA) affect clock behavior. CPOL=0 means the clock idles low; CPOL=1 means it idles high. CPHA=0 samples data on the leading clock edge, while CPHA=1 samples on the trailing edge. The execution table traces steps for each CPOL and CPHA combination, showing clock levels and when data is sampled. Variable tracking shows how CPOL, CPHA, clock level, and sample edge change step by step. Key moments clarify common confusions about idle clock level and sampling timing. The quiz tests understanding of clock idle state and sampling edges. This helps beginners see exactly how CPOL and CPHA control SPI timing for correct data transfer.

Practice

1.

What does the CPOL setting control in SPI communication?

easy

A. The speed of the clock signal

B. The idle level of the clock signal (high or low)

C. The data bit order (MSB or LSB first)

D. The voltage level of the data line

Solution

1. Step 1: Understand CPOL meaning

   CPOL stands for Clock Polarity and it defines the idle state of the clock line in SPI communication.

2. Step 2: Identify what CPOL controls

   CPOL sets whether the clock signal is low or high when idle (not toggling).

3. Final Answer:

   The idle level of the clock signal (high or low) -> Option B

4. Quick Check:

   CPOL = Clock idle level [OK]

Hint: CPOL = Clock idle level, remember idle means 'rest' state [OK]

Common Mistakes:

• Confusing CPOL with clock speed
• Thinking CPOL controls data order
• Mixing CPOL with voltage levels

2.

Which of the following is the correct way to set CPHA to 1 in embedded C?

SPI->CR1 = ...;

easy

A. SPI->CR1 |= (1 << 1);

B. SPI->CR1 |= (1 << 2);

C. SPI->CR1 |= (1 << 0);

D. SPI->CR1 |= (1 << 3);

Solution

1. Step 1: Identify CPHA bit position

   In many SPI controllers, CPHA is bit 1 (second bit) in the control register.

2. Step 2: Set CPHA bit correctly

   Setting CPHA to 1 means setting bit 1, so use (1 << 1) to set that bit.

3. Final Answer:

   SPI->CR1 |= (1 << 1); -> Option A

4. Quick Check:

   CPHA bit = 1 << 1 [OK]

Hint: CPHA usually bit 1, so shift 1 by 1 [OK]

Common Mistakes:

• Using wrong bit shift for CPHA
• Confusing CPHA with CPOL bit position
• Forgetting to use bitwise OR to set bit

3.

Given the following code snippet, what is the SPI mode configured?

SPI->CR1 = (1 << 1) | (1 << 0);

Assuming bit 0 = CPOL and bit 1 = CPHA.

medium

A. CPOL=0, CPHA=1 (Mode 1)

B. CPOL=1, CPHA=0 (Mode 2)

C. CPOL=1, CPHA=1 (Mode 3)

D. CPOL=0, CPHA=0 (Mode 0)

Solution

1. Step 1: Decode bits from CR1 value

   The value sets bit 0 and bit 1 to 1, so CPOL=1 and CPHA=1.

2. Step 2: Match CPOL and CPHA to SPI mode

   CPOL=1 and CPHA=1 corresponds to SPI Mode 3.

3. Final Answer:

   CPOL=1, CPHA=1 (Mode 3) -> Option C

4. Quick Check:

   Bits 0 and 1 set = CPOL=1, CPHA=1 [OK]

Hint: Bit 0 = CPOL, bit 1 = CPHA, both 1 means Mode 3 [OK]

Common Mistakes:

• Mixing up which bit is CPOL or CPHA
• Confusing SPI mode numbers
• Ignoring bit positions in register

4.

Identify the error in this SPI configuration code snippet:

SPI->CR1 = (1 << 2); // Set CPHA to 1

Assuming CPHA is bit 1 and CPOL is bit 0.

medium

A. CPHA bit is incorrectly set at bit 2 instead of bit 1

B. CPOL bit should be set before CPHA

C. The code should clear other bits before setting CPHA

D. CPHA cannot be set using bit shifts

Solution

1. Step 1: Check CPHA bit position

   CPHA is bit 1, but code sets bit 2, which is incorrect.

2. Step 2: Understand correct bit setting

   To set CPHA, bit 1 must be set using (1 << 1), not (1 << 2).

3. Final Answer:

   CPHA bit is incorrectly set at bit 2 instead of bit 1 -> Option A

4. Quick Check:

   CPHA = bit 1, code sets bit 2 [OK]

Hint: CPHA is bit 1, not bit 2; check bit positions carefully [OK]

Common Mistakes:

• Setting wrong bit for CPHA
• Assuming CPHA is bit 2 by mistake
• Not verifying hardware documentation

5.

You need to configure SPI to Mode 0 (CPOL=0, CPHA=0) but your device only works if data is sampled on the second clock edge. How should you set CPOL and CPHA?

hard

A. CPOL=0, CPHA=0 to sample on second edge

B. CPOL=1, CPHA=0 to sample on second edge

C. CPOL=1, CPHA=1 to sample on second edge

D. CPOL=0, CPHA=1 to sample on second edge

Solution

1. Step 1: Understand SPI Mode 0 settings

   Mode 0 means CPOL=0 (clock idle low) and CPHA=0 (sample on first edge).

2. Step 2: Adjust CPHA to sample on second edge

   To sample on the second clock edge, CPHA must be set to 1, keeping CPOL=0.

3. Step 3: Confirm final settings

   Set CPOL=0 and CPHA=1 to keep clock idle low but sample on second edge.

4. Final Answer:

   CPOL=0, CPHA=1 to sample on second edge -> Option D

5. Quick Check:

   Sample second edge = CPHA=1 [OK]

Hint: CPHA=1 means sample on second edge, CPOL controls idle level [OK]

Common Mistakes:

• Assuming Mode 0 always means sample on first edge
• Changing CPOL when only CPHA needed
• Not knowing which edge is first or second