Clock polarity and phase (CPOL, CPHA) in Embedded C - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to set the clock polarity (CPOL) bit to 1.

Embedded C

SPI->CR1 |= (1 << [1]);

Drag options to blanks, or click blank then click option'

A2

B1

C0

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using bit 0 instead of bit 1 for CPOL.

Confusing CPOL with CPHA bit positions.

The CPOL bit is usually bit 1 in the SPI control register CR1. Setting it to 1 configures the clock polarity.

2fill in blank

medium

Complete the code to clear the clock phase (CPHA) bit.

Embedded C

SPI->CR1 &= ~(1 << [1]);

Drag options to blanks, or click blank then click option'

A3

B1

C2

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Clearing the wrong bit position.

Using |= instead of &=~ to clear the bit.

The CPHA bit is usually bit 0 in the SPI control register CR1. Clearing it sets the clock phase to 0.

3fill in blank

hard

Fix the error in the code to set CPOL and CPHA correctly.

Embedded C

SPI->CR1 = (1 << [1]) | (1 << [2]);

Drag options to blanks, or click blank then click option'

A0

B1

C2

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Setting wrong bit positions for CPOL or CPHA.

Using assignment instead of bitwise OR.

CPOL is bit 1 and CPHA is bit 0. The code should set both bits 1 and 0.

4fill in blank

hard

Fill both blanks to configure SPI with CPOL=1 and CPHA=0 using bitwise operations.

Embedded C

SPI->CR1 = (1 << [1]) & ~(1 << [2]);

Drag options to blanks, or click blank then click option'

A1

B0

C2

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using OR instead of AND to clear a bit.

Mixing up CPOL and CPHA bit positions.

Set CPOL (bit 1) by shifting 1 left by 1, and clear CPHA (bit 0) by clearing bit 0.

5fill in blank

hard

Fill all three blanks to create a mask that sets CPOL and CPHA bits and clears bit 2.

Embedded C

SPI->CR1 = ((1 << [1]) | (1 << [2])) & ~(1 << [3]);

Drag options to blanks, or click blank then click option'

A1

B0

C2

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Not using parentheses causing wrong bitwise precedence.

Setting bit 2 instead of clearing it.

Set CPOL (bit 1) and CPHA (bit 0), and clear bit 2 to disable unwanted features.

Practice

1.

What does the CPOL setting control in SPI communication?

easy

A. The speed of the clock signal

B. The idle level of the clock signal (high or low)

C. The data bit order (MSB or LSB first)

D. The voltage level of the data line

Solution

1. Step 1: Understand CPOL meaning

   CPOL stands for Clock Polarity and it defines the idle state of the clock line in SPI communication.

2. Step 2: Identify what CPOL controls

   CPOL sets whether the clock signal is low or high when idle (not toggling).

3. Final Answer:

   The idle level of the clock signal (high or low) -> Option B

4. Quick Check:

   CPOL = Clock idle level [OK]

Hint: CPOL = Clock idle level, remember idle means 'rest' state [OK]

Common Mistakes:

• Confusing CPOL with clock speed
• Thinking CPOL controls data order
• Mixing CPOL with voltage levels

2.

Which of the following is the correct way to set CPHA to 1 in embedded C?

SPI->CR1 = ...;

easy

A. SPI->CR1 |= (1 << 1);

B. SPI->CR1 |= (1 << 2);

C. SPI->CR1 |= (1 << 0);

D. SPI->CR1 |= (1 << 3);

Solution

1. Step 1: Identify CPHA bit position

   In many SPI controllers, CPHA is bit 1 (second bit) in the control register.

2. Step 2: Set CPHA bit correctly

   Setting CPHA to 1 means setting bit 1, so use (1 << 1) to set that bit.

3. Final Answer:

   SPI->CR1 |= (1 << 1); -> Option A

4. Quick Check:

   CPHA bit = 1 << 1 [OK]

Hint: CPHA usually bit 1, so shift 1 by 1 [OK]

Common Mistakes:

• Using wrong bit shift for CPHA
• Confusing CPHA with CPOL bit position
• Forgetting to use bitwise OR to set bit

3.

Given the following code snippet, what is the SPI mode configured?

SPI->CR1 = (1 << 1) | (1 << 0);

Assuming bit 0 = CPOL and bit 1 = CPHA.

medium

A. CPOL=0, CPHA=1 (Mode 1)

B. CPOL=1, CPHA=0 (Mode 2)

C. CPOL=1, CPHA=1 (Mode 3)

D. CPOL=0, CPHA=0 (Mode 0)

Solution

1. Step 1: Decode bits from CR1 value

   The value sets bit 0 and bit 1 to 1, so CPOL=1 and CPHA=1.

2. Step 2: Match CPOL and CPHA to SPI mode

   CPOL=1 and CPHA=1 corresponds to SPI Mode 3.

3. Final Answer:

   CPOL=1, CPHA=1 (Mode 3) -> Option C

4. Quick Check:

   Bits 0 and 1 set = CPOL=1, CPHA=1 [OK]

Hint: Bit 0 = CPOL, bit 1 = CPHA, both 1 means Mode 3 [OK]

Common Mistakes:

• Mixing up which bit is CPOL or CPHA
• Confusing SPI mode numbers
• Ignoring bit positions in register

4.

Identify the error in this SPI configuration code snippet:

SPI->CR1 = (1 << 2); // Set CPHA to 1

Assuming CPHA is bit 1 and CPOL is bit 0.

medium

A. CPHA bit is incorrectly set at bit 2 instead of bit 1

B. CPOL bit should be set before CPHA

C. The code should clear other bits before setting CPHA

D. CPHA cannot be set using bit shifts

Solution

1. Step 1: Check CPHA bit position

   CPHA is bit 1, but code sets bit 2, which is incorrect.

2. Step 2: Understand correct bit setting

   To set CPHA, bit 1 must be set using (1 << 1), not (1 << 2).

3. Final Answer:

   CPHA bit is incorrectly set at bit 2 instead of bit 1 -> Option A

4. Quick Check:

   CPHA = bit 1, code sets bit 2 [OK]

Hint: CPHA is bit 1, not bit 2; check bit positions carefully [OK]

Common Mistakes:

• Setting wrong bit for CPHA
• Assuming CPHA is bit 2 by mistake
• Not verifying hardware documentation

5.

You need to configure SPI to Mode 0 (CPOL=0, CPHA=0) but your device only works if data is sampled on the second clock edge. How should you set CPOL and CPHA?

hard

A. CPOL=0, CPHA=0 to sample on second edge

B. CPOL=1, CPHA=0 to sample on second edge

C. CPOL=1, CPHA=1 to sample on second edge

D. CPOL=0, CPHA=1 to sample on second edge

Solution

1. Step 1: Understand SPI Mode 0 settings

   Mode 0 means CPOL=0 (clock idle low) and CPHA=0 (sample on first edge).

2. Step 2: Adjust CPHA to sample on second edge

   To sample on the second clock edge, CPHA must be set to 1, keeping CPOL=0.

3. Step 3: Confirm final settings

   Set CPOL=0 and CPHA=1 to keep clock idle low but sample on second edge.

4. Final Answer:

   CPOL=0, CPHA=1 to sample on second edge -> Option D

5. Quick Check:

   Sample second edge = CPHA=1 [OK]

Hint: CPHA=1 means sample on second edge, CPOL controls idle level [OK]

Common Mistakes:

• Assuming Mode 0 always means sample on first edge
• Changing CPOL when only CPHA needed
• Not knowing which edge is first or second