Complete the code to enable SWO output for printf in ARM Cortex-M.
CoreDebug->DEMCR |= [1];The DEMCR register's TRCENA bit enables the trace and debug blocks, which is necessary for SWO output.
Complete the code to unlock the ITM stimulus port for SWO printf output.
ITM->LAR = [1];The ITM Lock Access Register (LAR) must be written with the key 0xC5ACCE55 to unlock ITM registers for writing.
Fix the error in enabling the ITM stimulus port 0 for printf output.
ITM->TER |= [1];Setting bit 0 in the ITM Trace Enable Register (TER) enables stimulus port 0, which is used for printf output via SWO.
Fill both blanks to configure the TPIU for SWO output at 2 MHz.
TPI->ACPR = [1]; // Set prescaler TPI->SPPR = [2]; // Select protocol
The prescaler divides the core clock to get 2 MHz SWO speed; for 80 MHz core clock, prescaler is 39 (80/2 -1). SPPR=1 selects NRZ protocol for SWO.
Fill all three blanks to enable ITM, configure stimulus port, and unlock ITM for SWO printf.
CoreDebug->DEMCR |= [1]; ITM->LAR = [2]; ITM->TER |= [3];
First, enable trace in DEMCR with TRCENA bit. Then unlock ITM with key 0xC5ACCE55. Finally, enable stimulus port 0 by setting bit 0 in TER.
