Pipeline stalls and hazards in ARM Architecture - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a pipeline stall in ARM architecture?

A pipeline stall is a delay in the instruction pipeline where the processor must wait before executing the next instruction. This happens to avoid errors caused by data or control hazards.

beginner

Define a data hazard in the context of pipeline processing.

A data hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed, causing a potential conflict in the pipeline.

intermediate

What is a control hazard and how does it affect the pipeline?

A control hazard happens when the pipeline makes wrong decisions on branch instructions, causing it to fetch incorrect instructions and requiring correction, which stalls the pipeline.

intermediate

How do pipeline hazards cause stalls?

Hazards cause stalls because the pipeline must pause to resolve conflicts or wait for data, preventing smooth instruction flow and reducing performance temporarily.

intermediate

Name one common technique to reduce pipeline stalls in ARM processors.

One common technique is forwarding (also called bypassing), which sends data directly from one pipeline stage to another to avoid waiting for it to be written back to registers.

What causes a data hazard in a pipeline?

A A branch instruction changes the flow of execution

B The instruction cache is full

C The processor runs out of power

D An instruction uses data not yet produced by a previous instruction

Data hazards occur when an instruction needs data that a previous instruction has not yet finished producing.

What is the main effect of a pipeline stall?

A The processor speeds up

B The processor shuts down

C The pipeline pauses and delays instruction execution

D The pipeline skips instructions

A stall causes the pipeline to pause, delaying the execution of instructions to avoid errors.

Which hazard is related to branch instructions?

A Control hazard

B Structural hazard

C Data hazard

D Memory hazard

Control hazards happen when the pipeline encounters branch instructions that change the flow of execution.

What technique helps reduce stalls caused by data hazards?

A Increasing clock speed

B Forwarding

C Adding more registers

D Using larger caches

Forwarding sends data directly between pipeline stages to avoid waiting and reduce stalls.

Why do pipeline stalls reduce processor performance?

A They delay instruction execution, reducing throughput

B They make the processor skip instructions

C They increase power consumption

D They cause the processor to overheat

Stalls delay instruction execution, which lowers the number of instructions completed per time unit.

Explain what pipeline stalls and hazards are, and why they occur in ARM processors.

Think about how instructions depend on each other and how branches affect the flow.

Describe one method used in ARM architecture to reduce pipeline stalls and how it works.

Consider how data can be shared quickly without waiting for the usual steps.

Practice

1. What is the main reason for a pipeline stall in ARM architecture?

easy

A. The memory is too fast

B. The processor runs out of power

C. An instruction must wait due to a hazard to avoid errors

D. The program has no instructions left

Solution

1. Step 1: Understand what a pipeline stall means

   A pipeline stall occurs when the processor must pause instruction execution to prevent errors.

2. Step 2: Identify the cause of the stall

   Stalls happen because of hazards, which force instructions to wait to keep correct operation.

3. Final Answer:

   An instruction must wait due to a hazard to avoid errors -> Option C

4. Quick Check:

   Pipeline stall = waiting due to hazard [OK]

Hint: Stalls happen when instructions must wait to avoid errors [OK]

Common Mistakes:

• Thinking stalls happen because of power or memory speed
• Confusing stalls with program end
• Assuming stalls are caused by hardware failure

2. Which of the following is the correct term for a hazard that occurs when two instructions need the same hardware resource at the same time?

easy

A. Data hazard

B. Memory hazard

C. Control hazard

D. Structural hazard

Solution

1. Step 1: Recall types of hazards

   Hazards include data, structural, and control hazards.

2. Step 2: Identify hazard by resource conflict

   Structural hazard happens when hardware resources are needed by multiple instructions simultaneously.

3. Final Answer:

   Structural hazard -> Option D

4. Quick Check:

   Resource conflict = Structural hazard [OK]

Hint: Resource conflicts cause structural hazards [OK]

Common Mistakes:

• Mixing data hazard with resource conflicts
• Confusing control hazard with hardware resource issues
• Assuming memory hazard is a standard hazard type

3. Consider this simplified ARM pipeline sequence: Instruction 1 writes to register R1, Instruction 2 reads from R1 immediately after. What happens if there is no hazard management?

medium

A. Instruction 2 reads an old value from R1 causing incorrect results

B. Instruction 2 skips reading R1

C. The processor stalls automatically and waits

D. Instruction 2 reads the correct updated value from R1

Solution

1. Step 1: Understand data hazard in pipeline

   Instruction 2 depends on the result of Instruction 1, which updates R1.

2. Step 2: Effect of no hazard management

   Without hazard management, Instruction 2 reads R1 before Instruction 1 writes the new value, so it reads old data.

3. Final Answer:

   Instruction 2 reads an old value from R1 causing incorrect results -> Option A

4. Quick Check:

   Data hazard without fix = wrong read [OK]

Hint: Without hazard fix, dependent reads get old data [OK]

Common Mistakes:

• Assuming processor stalls automatically without hazard logic
• Thinking Instruction 2 skips reading register
• Believing Instruction 2 always reads updated value

4. In an ARM pipeline, a control hazard occurs due to a branch instruction. Which fix helps reduce stalls caused by this hazard?

medium

A. Using branch prediction to guess the next instruction

B. Increasing the clock speed

C. Adding more registers

D. Disabling the pipeline

Solution

1. Step 1: Identify control hazard cause

   Control hazards happen when the pipeline must decide which instruction to execute after a branch.

2. Step 2: Understand branch prediction role

   Branch prediction guesses the next instruction to reduce waiting and stalls.

3. Final Answer:

   Using branch prediction to guess the next instruction -> Option A

4. Quick Check:

   Branch prediction reduces control stalls [OK]

Hint: Branch prediction reduces control hazard stalls [OK]

Common Mistakes:

• Thinking clock speed fixes hazards
• Believing more registers solve control hazards
• Assuming disabling pipeline is a solution

5. You have a sequence of instructions where Instruction A writes to register R2, Instruction B reads R2, and Instruction C is a branch depending on R2. How can pipeline stalls be minimized in this scenario?

hard

A. Insert NOPs (no operation) between all instructions

B. Use forwarding to pass data directly and branch prediction for the branch

C. Disable branch instructions to avoid control hazards

D. Increase pipeline stages to slow down execution

Solution

1. Step 1: Identify hazards in instruction sequence

   Instruction B reading R2 after A causes a data hazard; Instruction C branch depending on R2 causes a control hazard.

2. Step 2: Apply techniques to reduce stalls

   Forwarding passes updated data directly to dependent instructions, and branch prediction guesses branch outcome to reduce stalls.

3. Final Answer:

   Use forwarding to pass data directly and branch prediction for the branch -> Option B

4. Quick Check:

   Forwarding + branch prediction minimize stalls [OK]

Hint: Forwarding and branch prediction reduce stalls best [OK]

Common Mistakes:

• Inserting too many NOPs causing slow execution
• Disabling branches which breaks program logic
• Increasing pipeline stages without hazard fixes