ITM (Instrumentation Trace Macrocell) in ARM Architecture - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to enable the ITM by setting the correct bit in the control register.

ARM Architecture

ITM->[1] = 1;

Drag options to blanks, or click blank then click option'

ATER

BPORT

CTPR

DTCR

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing the Trace Enable Register (TER) with the Control Register (TCR).

Trying to enable ITM by writing to the wrong register.

The ITM Control Register (TCR) is used to enable the ITM. Setting it to 1 enables the ITM.

2fill in blank

medium

Complete the code to check if ITM Port 0 is enabled before sending data.

ARM Architecture

if (ITM->[1] & 1) { send_data(); }

Drag options to blanks, or click blank then click option'

ATER

BTCR

CTPR

DPORT

Attempts:

3 left

💡 Hint

Common Mistakes

Checking the wrong register like TCR or TPR instead of TER.

Not masking the correct bit for Port 0.

The Trace Enable Register (TER) controls which stimulus ports are enabled. Checking bit 0 of TER tells if Port 0 is enabled.

3fill in blank

hard

Fix the error in the code to write a byte to ITM Port 1 correctly.

ARM Architecture

while (ITM->[1][1] == 0) {} ITM->[1][1] = data;

Drag options to blanks, or click blank then click option'

APORT

BTCR

CTPR

DTER

Attempts:

3 left

💡 Hint

Common Mistakes

Using TER, which enables the port but does not indicate current readiness.

Checking TCR or TPR instead of the PORT register.

When read, the ITM PORT[1] register returns a non-zero value if Port 1 is enabled in TER and ready to accept data. The while loop polls until ready.

4fill in blank

hard

Fill both blanks to configure ITM to enable Port 2 and set the privilege level.

ARM Architecture

ITM->[1] |= (1 << 2); ITM->[2] = 0x0;

Drag options to blanks, or click blank then click option'

ATER

BTCR

CTPR

DPORT

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up TER and TCR registers.

Setting privilege in the wrong register.

Setting bit 2 in TER enables Port 2. The TPR (Trace Privilege Register) set to 0x0 configures privileged access only.

5fill in blank

hard

Fill all three blanks to create a dictionary comprehension that maps ITM ports to their enable status for ports 0 to 2.

ARM Architecture

port_status = {{'{'}}[1]: bool(ITM->TER & (1 << [2])) for [3] in range(3){{'}}'}}

Drag options to blanks, or click blank then click option'

Aport

Bi

Attempts:

3 left

💡 Hint

Common Mistakes

Using different variable names inconsistently.

Using a variable name not defined in the loop.

The variable 'i' is used as the loop variable and key in the dictionary. The expression checks if bit i in TER is set, indicating if port i is enabled.

Practice

1. What is the primary purpose of the ITM (Instrumentation Trace Macrocell) in ARM architecture?

easy

A. To manage memory allocation dynamically

B. To increase the clock speed of the processor

C. To monitor program execution without stopping the program

D. To handle input/output operations directly

Solution

1. Step 1: Understand ITM's role in ARM

   ITM is designed to trace and monitor program actions during execution.

2. Step 2: Identify its key feature

   It allows watching program behavior without stopping or interrupting the program.

3. Final Answer:

   To monitor program execution without stopping the program -> Option C

4. Quick Check:

   ITM = Monitor without stopping [OK]

Hint: ITM watches program live without pause [OK]

Common Mistakes:

• Confusing ITM with processor speed control
• Thinking ITM manages memory
• Assuming ITM handles I/O operations

2. Which of the following is the correct way to send a message using ITM in ARM assembly?

easy

A. Read data from ITM control register

B. Disable ITM before sending data

C. Set the ITM clock speed register

D. Write data to ITM stimulus port register

Solution

1. Step 1: Identify ITM message sending method

   ITM sends messages by writing data to its stimulus port registers.

2. Step 2: Eliminate incorrect options

   Reading control registers or disabling ITM does not send messages; setting clock speed is unrelated.

3. Final Answer:

   Write data to ITM stimulus port register -> Option D

4. Quick Check:

   Send message = Write to stimulus port [OK]

Hint: Send messages by writing to stimulus port [OK]

Common Mistakes:

• Trying to send by reading registers
• Confusing control register with data port
• Disabling ITM before sending

3. Given the following pseudo-code using ITM stimulus port 0:

ITM_STIM0 = 0x41;  // Send ASCII 'A'
ITM_STIM0 = 0x42;  // Send ASCII 'B'

What sequence of characters will the debugger receive?

medium

A. AB

B. BA

C. A only

D. No output

Solution

1. Step 1: Analyze the writes to ITM stimulus port

   The code writes 0x41 ('A') then 0x42 ('B') sequentially to the ITM port.

2. Step 2: Understand ITM output behavior

   ITM sends each written byte in order to the debugger, so output is 'A' followed by 'B'.

3. Final Answer:

   AB -> Option A

4. Quick Check:

   Write order = output order [OK]

Hint: Output matches write sequence to ITM port [OK]

Common Mistakes:

• Assuming output reverses order
• Thinking only first write sends data
• Believing ITM buffers and drops data

4. A developer writes to ITM stimulus port but sees no output in the debugger. Which is the most likely cause?

medium

A. The program is running in user mode

B. ITM is not enabled or unlocked

C. The debugger is not connected to UART

D. The CPU clock speed is too high

Solution

1. Step 1: Check ITM configuration requirements

   ITM must be enabled and unlocked before it can send data.

2. Step 2: Evaluate other options

   CPU speed or user mode does not prevent ITM output; debugger connection to UART is unrelated to ITM trace ports.

3. Final Answer:

   ITM is not enabled or unlocked -> Option B

4. Quick Check:

   ITM enabled = output visible [OK]

Hint: Enable ITM before sending data [OK]

Common Mistakes:

• Ignoring ITM enable status
• Blaming CPU speed
• Confusing debugger UART with ITM trace

5. How can ITM be used to efficiently debug an embedded system without affecting its real-time performance?

hard

A. By sending trace data asynchronously through stimulus ports to a debugger

B. By halting the processor frequently to inspect registers

C. By logging data to internal RAM and reading after execution

D. By disabling interrupts during debugging

Solution

1. Step 1: Understand ITM's asynchronous tracing

   ITM sends trace data asynchronously via stimulus ports, avoiding program interruption.

2. Step 2: Compare with other debugging methods

   Halting processor or disabling interrupts affects real-time behavior; logging to RAM delays data access.

3. Final Answer:

   By sending trace data asynchronously through stimulus ports to a debugger -> Option A

4. Quick Check:

   Asynchronous trace = real-time debug [OK]

Hint: Use ITM's async ports for real-time debug [OK]

Common Mistakes:

• Stopping processor to debug
• Disabling interrupts during tests
• Relying on post-run RAM logs