ARM Architecture - Exception and Interrupt Model
Consider this simplified ARM exception entry sequence:
What will be the value of PC after step 4 if the exception vector address is 0x00000010?
1. Save CPSR to SPSR
2. Save return address to LR
3. Switch to exception mode
4. Set PC to exception vector
What will be the value of PC after step 4 if the exception vector address is 0x00000010?
