[Solved] An engineer writes this code to enter deep sleep: MRS R0, SCR ORR R0, R0, #0x2 MSR SCR, R0 WFI Why might this fail to enter deep sleep mode? | ARM Architecture

ARM Architecture - Power Modes

An engineer writes this code to enter deep sleep:

    MRS R0, SCR
    ORR R0, R0, #0x2
    MSR SCR, R0
    WFI

Why might this fail to enter deep sleep mode?

AMSR instruction is invalid

BWFI instruction is missing

CThe wrong bit (0x2) is set; SLEEPDEEP is bit 2 (0x4)

DSCR register cannot be read

Step-by-Step Solution

Solution:

Step 1: Identify correct SLEEPDEEP bit
SLEEPDEEP is bit 2 (value 0x4), not bit 1 (0x2).
Step 2: Analyze code's bit set
Setting 0x2 sets the wrong bit, so deep sleep mode is not enabled.
Final Answer:
The wrong bit (0x2) is set; SLEEPDEEP is bit 2 (0x4) -> Option C
Quick Check:
Correct bit = 0x4, not 0x2 = D [OK]

Quick Trick: SLEEPDEEP bit is 0x4, not 0x2 [OK]

Common Mistakes:

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An engineer writes this code to enter deep sleep: