Transitionready → running pid:B - Process B dispatched to CPU
A
ready
burst: 9
B
running
burst: 8
Ready Queue
A
Waiting Queue
empty
🖥CPUBt=3
A
A.T1
Transitionrunning → running pid:B - Process B executed 1 time unit
A
ready
burst: 9
B
running
burst: 7
Ready Queue
A
Waiting Queue
empty
🖥CPUBt=4
A
A.T1
B
Transitionready → running pid:A - Process A dispatched to CPU
A
running
burst: 9
B
ready
burst: 7
Ready Queue
B
Waiting Queue
empty
🖥CPUAt=4
A
A.T1
B
Transitionrunning → terminated pid:A - Process A completed execution and terminated
B
ready
burst: 7
Ready Queue
B
Waiting Queue
empty
🖥CPUidlet=5
A
A.T1
B
A
Transitionrunning → terminated pid:B - Process B completed execution and terminated
Ready Queue
empty
Waiting Queue
empty
🖥CPUidlet=13
A
A.T1
B
A
B
Key Takeaways
✓ Processes have independent memory and resources, while threads share the process's resources but have separate execution contexts.
This difference is often abstract in code but becomes clear when watching resource allocation and scheduling side-by-side.
✓ Threads are scheduled independently but run within the context of their parent process, allowing lightweight concurrency.
Seeing threads enter ready and running states within the same process clarifies how they differ from full processes.
✓ CPU scheduling switches between processes and threads, demonstrating context switching and resource sharing in action.
Visualizing scheduling decisions helps understand how the OS manages multitasking and resource allocation.
Practice
(1/5)
1. When a timer interrupt triggers a context switch, what is the correct sequence of events that occur internally before the next process runs?
easy
A. Scheduler selects next process -> Save current CPU registers -> Load next process PCB registers -> Resume execution
B. Save current CPU registers to PCB -> Load next process PCB registers -> Scheduler selects next process -> Resume execution
C. Save current CPU registers to PCB -> Scheduler selects next process -> Load next process PCB registers -> Resume execution
D. Load next process PCB registers -> Save current CPU registers -> Scheduler selects next process -> Resume execution
Solution
Step 1: Save current process state
Before switching, CPU registers of the current process must be saved to its PCB.
Step 2: Scheduler decision
After saving, the scheduler selects the next process to run.
Step 3: Load next process state
The CPU registers of the selected process are loaded from its PCB.
Step 4: Resume execution
The CPU resumes execution with the new process context.
Final Answer:
Option C -> Option C
Quick Check:
Saving registers before scheduler decision and loading registers after is the correct order.
Hint: Save first, then schedule, then load -> context switch order [OK]
Common Mistakes:
Selecting next process before saving current registers
Loading next process registers before scheduler decision
Mixing order of save/load and scheduling
2. In which scenario is preemptive Shortest Job First (SJF) scheduling preferred over non-preemptive SJF?
easy
A. When new processes with shorter burst times can arrive at any time during execution
B. When fairness is not a concern and starvation is acceptable
C. When minimizing context switch overhead is the highest priority
D. When all processes arrive at the same time and have similar burst times
Solution
Step 1: Understand preemptive SJF behavior
Preemptive SJF allows the CPU to switch to a newly arrived process if it has a shorter burst time than the currently running process.
Step 2: Analyze scenarios
If new processes with shorter burst times can arrive anytime, preemptive SJF ensures the CPU always runs the shortest job next, improving average waiting time.
Step 3: Why other options are incorrect
A: If all processes arrive simultaneously with similar burst times, preemptive advantage is minimal. B: Starvation is a concern in preemptive SJF, so it's not chosen when fairness is ignored. C: Preemptive SJF increases context switches, so it's not preferred when minimizing overhead.
Final Answer:
Option A -> Option A
Quick Check:
Preemptive SJF is best when shorter jobs can arrive anytime, requiring immediate preemption.
Hint: Preemptive SJF shines when shorter jobs arrive unpredictably [OK]
Common Mistakes:
Assuming preemptive SJF always reduces overhead
Believing preemptive SJF is best when all jobs arrive simultaneously
3. Which of the following statements about Peterson's algorithm is INCORRECT?
medium
A. It can be extended straightforwardly to more than two processes
B. It guarantees mutual exclusion between two processes
C. It ensures progress and bounded waiting
D. It does not require special hardware instructions
Solution
Step 1: Verify correctness of each statement
Options A, C, and D are true properties of Peterson's algorithm.
Step 2: Identify incorrect statement
It can be extended straightforwardly to more than two processes is incorrect because Peterson's algorithm is specifically designed for two processes and does not extend easily to multiple processes.
Final Answer:
Option A -> Option A
Quick Check:
Peterson's algorithm is a two-process solution only.
Hint: Peterson's = two-process only, no hardware needed, guarantees progress
Common Mistakes:
Assuming easy extension to multiple processes
Confusing bounded waiting with starvation
Believing hardware instructions are required
4. Which of the following statements about Effective Access Time (EAT) in systems using TLB is INCORRECT?
medium
A. A TLB miss always causes a page fault, increasing EAT drastically
B. EAT depends on both TLB hit ratio and memory access time
C. EAT can be calculated as (TLB hit ratio x TLB access time) + (TLB miss ratio x page table access time)
D. Improving TLB hit ratio reduces the average memory access time
Solution
Step 1: Recall EAT formula
EAT = (hit ratio x access time on hit) + (miss ratio x access time on miss)
Step 2: Analyze each statement
A: Correct, EAT depends on hit ratio and memory times. B: Incorrect, TLB miss does not always cause page fault; it triggers page table lookup. C: Correct, formula reflects hit and miss costs. D: Correct, higher hit ratio lowers average access time.
Final Answer:
Option A -> Option A
Quick Check:
TLB miss ≠ page fault; page fault only if page not in memory.
Hint: TLB miss ≠ page fault; page fault only if page absent [OK]
Common Mistakes:
Confusing TLB miss with page fault
Misapplying EAT formula
5. If Peterson's algorithm is used on a modern multi-core processor with weak memory ordering (e.g., relaxed memory consistency), what is a likely issue that can arise, and how can it be addressed?
hard
A. The algorithm will cause starvation because weak memory ordering breaks bounded waiting
B. The algorithm will cause deadlock because weak memory ordering delays flag updates
C. The algorithm will work correctly without modification because it uses only atomic variables
D. The algorithm may fail mutual exclusion due to instruction reordering; inserting memory barriers can fix this
Solution
Step 1: Understand weak memory ordering impact
Modern processors may reorder instructions, causing visibility issues for shared variables.
Step 2: Effect on Peterson's algorithm
Without memory barriers, the flags and turn variables may be seen out of order, breaking mutual exclusion.
Step 3: Solution
Inserting memory fences/barriers enforces ordering and visibility, preserving correctness.
Final Answer:
Option D -> Option D
Quick Check:
Memory barriers are essential on weakly ordered architectures for software synchronization.
Hint: Weak memory ordering -> need memory barriers for Peterson's correctness
Common Mistakes:
Assuming Peterson's works without modification on all hardware