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When implementing Peterson's algorithm on a modern multi-core processor with relaxed memory consistency, what is the primary concern that must be addressed to ensure correctness?

hard🚀 Advanced Concept Q8 of Q15
Operating Systems - Critical Section Problem - Requirements & Peterson's Solution
When implementing Peterson's algorithm on a modern multi-core processor with relaxed memory consistency, what is the primary concern that must be addressed to ensure correctness?
AExcessive CPU usage from busy waiting
BDeadlock due to infinite waiting on flags
CMemory reordering causing visibility issues between processes
DIncorrect initialization of the turn variable
Step-by-Step Solution
Solution:
  1. Step 1: Understand memory model

    Modern multi-core processors may reorder memory operations for optimization.
  2. Step 2: Impact on Peterson's algorithm

    This reordering can cause one process to see stale values of flags or turn, violating mutual exclusion.
  3. Step 3: Addressing the issue

    Memory barriers or fences are required to enforce ordering and visibility.
  4. Final Answer:

    Option C -> Option C
  5. Quick Check:

    Memory consistency affects synchronization correctness [OK]
Quick Trick: Memory reordering breaks flag visibility without fences [OK]
Common Mistakes:
MISTAKES
  • Confusing deadlock with memory visibility issues
  • Assuming busy waiting is the main problem
  • Ignoring the need for memory barriers
Trap Explanation:
PITFALL
  • Mistaking deadlock or CPU usage as primary issues instead of memory ordering
Interviewer Note:
CONTEXT
  • Tests knowledge of hardware memory models affecting software synchronization
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