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Steady-state error analysis in Simulink - Step-by-Step Execution

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Concept Flow - Steady-state error analysis
Define system and input
↓
Simulate system response
↓
Calculate output at steady state
↓
Calculate steady-state error = input - output
↓
Analyze error for different inputs
↓
Conclude system accuracy
The flow shows defining the system and input, simulating response, calculating steady-state output, then finding error and analyzing it.
Execution Sample
Simulink
step_input = 1;
output_ss = simulate_system(step_input);
steady_state_error = step_input - output_ss;
This code simulates the system with a step input and calculates the steady-state error as the difference between input and output.
Execution Table
StepInputSimulated OutputSteady-State OutputSteady-State ErrorAction
11 (step)0.8 (initial)Start simulation with step input
210.95 (approaching)System output rising
310.99 (near steady)Output close to steady state
411.0 (steady)1.00.0Calculate steady-state error = 1 - 1 = 0
52 (step)1.6 (initial)Change input to 2, simulate
621.9 (approaching)Output rising
721.99 (near steady)Output near steady state
822.0 (steady)2.00.0Calculate steady-state error = 2 - 2 = 0
9Ramp inputVariesSimulate ramp input for error analysis
10Ramp inputLess than inputOutput lags input, error > 0
11Ramp inputSteady state reachedCalculate steady-state error for ramp
12Ramp inputOutput < inputVariesPositiveError is positive, system not perfect for ramp
13End of simulation and analysis
💡 Simulation ends after analyzing steady-state error for step and ramp inputs.
Variable Tracker
VariableStartAfter Step InputAfter Step Input SteadyAfter Ramp InputAfter Ramp Input SteadyFinal
step_input011N/AN/A2
output_ss00.81.0VariesLess than input2.0
steady_state_errorN/AN/A0.0N/APositive0.0 or positive
Key Moments - 3 Insights
Why is the steady-state error zero for step inputs but positive for ramp inputs?
Because the system can perfectly track constant inputs (step), but cannot keep up with continuously increasing inputs (ramp), as shown in execution_table rows 4 and 12.
What does the steady-state output represent in the simulation?
It represents the output value after the system settles, used to calculate error by subtracting from input, as seen in execution_table rows 4 and 8.
Why do we simulate multiple input types (step, ramp) in steady-state error analysis?
Different inputs test system accuracy under various conditions; step tests constant input tracking, ramp tests tracking of changing inputs, shown in execution_table rows 1-8 and 9-12.
Visual Quiz - 3 Questions
Test your understanding
Look at the execution table, what is the steady-state error at step 4?
A0.2
B0.0
C1.0
DNot calculated yet
💡 Hint
Check the 'Steady-State Error' column at step 4 in the execution_table.
At which step does the simulation first show the output reaching steady state for input 2?
AStep 5
BStep 7
CStep 8
DStep 6
💡 Hint
Look for 'steady' output value for input 2 in the execution_table rows 5-8.
If the system output for ramp input perfectly matched the input, what would the steady-state error be?
AZero
BNegative
CPositive
DUndefined
💡 Hint
Refer to the definition of steady-state error as input minus output in variable_tracker.
Concept Snapshot
Steady-state error analysis:
- Simulate system response to input
- Find output after settling (steady state)
- Calculate error = input - output
- Zero error means perfect tracking
- Different inputs (step, ramp) test accuracy
- Useful to assess control system performance
Full Transcript
Steady-state error analysis involves simulating a system's response to inputs like step or ramp. We observe the output after it settles, called steady-state output. The error is the difference between input and output at this point. For step inputs, the error can be zero if the system tracks perfectly. For ramp inputs, error is often positive because the system lags. This analysis helps understand how well a system follows different inputs.

Practice

(1/5)
1. What does steady-state error in a Simulink control system represent?
easy
A. The initial delay before the system starts responding
B. The maximum output value during system response
C. The difference between the desired input and the actual output after the system settles
D. The time taken for the system to reach half of its final value

Solution

  1. Step 1: Understand steady-state error meaning

    Steady-state error measures how close the system output is to the input after settling.
  2. Step 2: Compare options with definition

    Only The difference between the desired input and the actual output after the system settles correctly describes this difference after settling.
  3. Final Answer:

    The difference between the desired input and the actual output after the system settles -> Option C
  4. Quick Check:

    Steady-state error = final input - final output [OK]
Hint: Steady-state error = input minus output after settling [OK]
Common Mistakes:
  • Confusing steady-state error with response time
  • Thinking it measures initial delay
  • Mixing it with peak output value
2. Which Simulink block is commonly used to measure steady-state error in a control system?
easy
A. Gain block
B. Sum block
C. Scope block
D. Integrator block

Solution

  1. Step 1: Identify block function

    The Sum block calculates the difference between signals, useful for error measurement.
  2. Step 2: Match block to steady-state error

    Steady-state error is the difference between input and output, so Sum block is used.
  3. Final Answer:

    Sum block -> Option B
  4. Quick Check:

    Sum block calculates error difference [OK]
Hint: Use Sum block to find difference between signals [OK]
Common Mistakes:
  • Choosing Scope block which only displays signals
  • Selecting Gain block which scales signals
  • Confusing Integrator block with error calculation
3. Given this MATLAB code snippet analyzing steady-state error in Simulink:
sys = tf([1], [1 3 2]);
y = step(sys, 10);
steady_error = abs(1 - y(end));
disp(steady_error);

What is the output of steady_error?
medium
A. 0.5
B. 1
C. 0
D. 2

Solution

  1. Step 1: Analyze transfer function and step response

    The transfer function G(s) = 1/(s^2 + 3s + 2) has DC gain G(0) = 1/2 = 0.5. Poles at -1 and -2 ensure stability, step response settles at 0.5.
  2. Step 2: Calculate steady-state error

    Steady-state error = abs(1 - final output) = |1 - 0.5| = 0.5.
  3. Final Answer:

    0.5 -> Option A
  4. Quick Check:

    DC gain = 1/2, error = |1 - 0.5| = 0.5 [OK]
Hint: Step response final value = DC gain for unit step [OK]
Common Mistakes:
  • Miscalculating DC gain as 1 instead of 1/2
  • Confusing transient response with steady-state
  • Thinking all stable systems have zero steady-state error
4. You have this Simulink model code snippet to calculate steady-state error:
sys = tf([2], [1 2 1]);
y = step(sys, 10);
steady_error = 1 - y(end);

Why might this code give a wrong steady-state error value?
medium
A. Because the variable y is not defined
B. Because the step function is called with wrong time
C. Because the transfer function numerator is incorrect
D. Because it does not take the absolute value of the error

Solution

  1. Step 1: Check error calculation formula

    The code calculates error as 1 - y(end) without absolute value, which can be negative.
  2. Step 2: Understand steady-state error definition

    Steady-state error should be absolute difference to represent magnitude correctly.
  3. Final Answer:

    Because it does not take the absolute value of the error -> Option D
  4. Quick Check:

    Error magnitude needs absolute value [OK]
Hint: Always use absolute value for steady-state error [OK]
Common Mistakes:
  • Ignoring sign of error
  • Assuming step time affects error calculation
  • Misdefining transfer function numerator
5. In a Simulink model, you want to reduce steady-state error for a system with transfer function G(s) = 1/(s+1). Which modification will most effectively reduce steady-state error to a step input?
hard
A. Add an integrator in the forward path
B. Increase the gain of the existing transfer function
C. Add a differentiator in the feedback path
D. Add a delay block before the output

Solution

  1. Step 1: Understand steady-state error for type 0 system

    G(s) = 1/(s+1) is type 0, which has nonzero steady-state error to step input.
  2. Step 2: Effect of adding integrator

    Adding an integrator (1/s) increases system type to 1, eliminating steady-state error for step inputs.
  3. Final Answer:

    Add an integrator in the forward path -> Option A
  4. Quick Check:

    Integrator reduces steady-state error to zero for step input [OK]
Hint: Add integrator to eliminate steady-state error for step input [OK]
Common Mistakes:
  • Thinking gain increase alone removes steady-state error
  • Confusing differentiator effect with error reduction
  • Adding delay which does not affect steady-state error
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