How to Design PCB for Ethernet: Key Steps and Best Practices

To design a PCB for Ethernet, ensure you use controlled impedance traces for differential pairs, maintain proper trace length matching, and place the magnetics close to the Ethernet PHY. Also, follow layout guidelines like separating analog and digital grounds and adding proper decoupling capacitors for signal integrity.

Syntax

Designing a PCB for Ethernet involves key elements such as:

• Controlled Impedance: Use differential pairs with specific trace width and spacing to maintain 100 ohm differential impedance.
• Trace Length Matching: Keep the lengths of differential pairs equal to avoid signal skew.
• Magnetics Placement: Place Ethernet magnetics (transformers) close to the PHY chip to reduce noise.
• Grounding: Separate analog and digital grounds and connect them at a single point.
• Decoupling Capacitors: Place capacitors near power pins to stabilize voltage.

c

/* Example controlled impedance calculation for differential pair */
// Trace width (W), spacing (S), and dielectric height (H) determine impedance
// Typical values for 100 ohm differential pair:
W = 6 mils;
S = 6 mils;
H = 5 mils;
// Use PCB design tool impedance calculator or formulas to verify

Example

This example shows a simple PCB layout snippet for an Ethernet differential pair with controlled impedance and matched trace lengths.

plaintext

Differential Pair Trace Layout:
- Trace Width: 6 mils
- Trace Spacing: 6 mils
- Trace Length: 50 mm (both traces equal)

Placement:
- Ethernet PHY at coordinate (10,10)
- Magnetics at (12,10) close to PHY

Ground:
- Analog ground plane below PHY
- Digital ground plane separated

Decoupling Capacitors:
- 0.1uF capacitor near PHY power pin

/* This layout ensures signal integrity and reduces noise */

Output

Visual PCB layout with matched differential pairs, magnetics close to PHY, and separated grounds.

Common Pitfalls

• Ignoring Impedance Control: Using incorrect trace width or spacing causes signal reflections and data errors.
• Unequal Trace Lengths: Leads to timing skew and degraded signal quality.
• Poor Magnetics Placement: Placing magnetics far from PHY increases noise and EMI.
• Mixed Grounds: Not separating analog and digital grounds can cause ground loops and interference.
• Insufficient Decoupling: Missing capacitors cause unstable power supply and signal glitches.

c

/* Wrong way: Unequal trace lengths */
Trace1_length = 50 mm;
Trace2_length = 60 mm; // causes skew

/* Right way: Matched trace lengths */
Trace1_length = 55 mm;
Trace2_length = 55 mm; // matched for signal integrity

Quick Reference

Design Aspect	Recommendation
Differential Pair Impedance	100 ohms differential controlled impedance
Trace Width & Spacing	Use PCB tool calculator, e.g., 6 mil width and 6 mil spacing
Trace Length Matching	Keep differential pair lengths equal within 5 mils
Magnetics Placement	Place magnetics close to Ethernet PHY chip
Grounding	Separate analog and digital grounds, connect at single point
Decoupling Capacitors	Place 0.1uF capacitors near power pins

Key Takeaways

Use controlled impedance differential pairs with matched trace lengths for Ethernet signals.

Place Ethernet magnetics close to the PHY to reduce noise and improve signal quality.

Separate analog and digital grounds to avoid interference and ground loops.

Add decoupling capacitors near power pins to stabilize voltage and reduce glitches.

Verify trace width and spacing with PCB impedance calculators for reliable Ethernet performance.