SPI data transfer sequence in Embedded C - Step-by-Step Execution

Concept Flow - SPI data transfer sequence

Start SPI Transfer

↓

Set CS Low (Select Slave)

↓

Load Data to SPI Data Register

↓

Wait for Transfer Complete Flag

↓

Read Received Data from SPI Data Register

↓

Set CS High (Deselect Slave)

↓

End SPI Transfer

This flow shows the steps of sending and receiving data over SPI: selecting the slave, sending data, waiting for completion, reading data, and deselecting the slave.

Execution Sample

Embedded C

CS_LOW();
SPI_DR = data_out;
while(!(SPI_SR & SPI_SR_TXE));
received = SPI_DR;
CS_HIGH();

This code sends one byte over SPI by selecting the slave, writing data, waiting for transmit complete, reading received data, and deselecting the slave.

Execution Table

Step	Action	SPI_SR (Status Register)	SPI_DR (Data Register)	CS Pin State	Result
1	CS_LOW() called	0x02	0x00	LOW	Slave selected, ready to send
2	SPI_DR = data_out (0x3A)	0x00	0x3A	LOW	Data loaded to send register
3	Wait for SPI_SR_TXE flag	0x02 (TXE set)	0x3A	LOW	Transmit buffer empty, transfer done
4	Read SPI_DR	0x02	0x5C	LOW	Received data 0x5C read
5	CS_HIGH() called	0x02	0x5C	HIGH	Slave deselected, transfer complete

💡 CS pin set HIGH, transfer sequence finished

Variable Tracker

Variable	Start	After Step 2	After Step 3	After Step 4	Final
SPI_SR	0x02	0x00	0x02	0x02	0x02
SPI_DR	0x00	0x3A	0x3A	0x5C	0x5C
CS Pin	HIGH	LOW	LOW	LOW	HIGH
received	undefined	undefined	undefined	0x5C	0x5C

Key Moments - 3 Insights

Why do we set CS pin LOW before sending data?

Setting CS LOW selects the slave device so it listens to SPI communication, as shown in step 1 of the execution_table.

What does waiting for the TXE flag mean?

Waiting for TXE means waiting until the transmit buffer is empty and data is sent, indicated by SPI_SR having the TXE bit set in step 3.

Why do we read SPI_DR after the transfer?

SPI is full-duplex; reading SPI_DR gets the data received from the slave during transmission, as done in step 4.

Visual Quiz - 3 Questions

Look at the execution_table, what is the CS pin state after step 3?

A HIGH

B LOW

C Undefined

D Toggling

💡 Hint

Check the 'CS Pin State' column at step 3 in execution_table.

At which step does the SPI_SR_TXE flag become set?

A Step 3

B Step 2

C Step 1

D Step 4

💡 Hint

Look at the 'SPI_SR' values in execution_table to find when TXE (0x02) appears.

If CS_HIGH() was called before reading SPI_DR, what would happen?

A SPI_SR_TXE flag would never set

B Slave might ignore the read, causing wrong data

C Data would still be read correctly

D SPI_DR would reset to zero

💡 Hint

Refer to key_moments about CS pin role and step 5 in execution_table.

Concept Snapshot

SPI Data Transfer Sequence:
1. Set CS LOW to select slave
2. Load data to SPI data register
3. Wait for TXE flag (transfer complete)
4. Read received data from SPI data register
5. Set CS HIGH to deselect slave
SPI is full-duplex: send and receive happen together.

Full Transcript

This visual trace shows the SPI data transfer sequence in embedded C. First, the chip select (CS) pin is set LOW to select the slave device. Then, data is loaded into the SPI data register (SPI_DR). The program waits until the transmit buffer empty (TXE) flag in the SPI status register (SPI_SR) is set, indicating the transfer is complete. Next, the received data is read from SPI_DR. Finally, the CS pin is set HIGH to deselect the slave and end the transfer. Variables like SPI_SR, SPI_DR, CS pin state, and received data change step-by-step as shown in the execution table and variable tracker. Key moments clarify why CS must be LOW during transfer, the meaning of the TXE flag, and why reading SPI_DR is necessary. The quiz tests understanding of pin states, flags, and sequence order. This sequence is essential for communicating with SPI devices in embedded systems.