Multi-level paging in Operating Systems - Practice Problems & Coding Challenges

Challenge - 5 Problems

🧠 Conceptual

intermediate

Understanding the purpose of multi-level paging

What is the main advantage of using multi-level paging in an operating system's memory management?

A It allows direct mapping of virtual addresses to physical addresses without translation.

B It eliminates the need for page replacement algorithms.

C It reduces the size of page tables by breaking them into smaller parts.

D It increases the size of the virtual address space beyond hardware limits.

💡 Hint

Think about how large page tables can be and what multi-level paging tries to solve.

Multi-level paging breaks large page tables into smaller, manageable pieces, reducing memory usage by only loading needed parts.

📋 Factual

intermediate

Number of page table accesses in two-level paging

In a two-level paging system, how many memory accesses are required to translate a virtual address to a physical address?

A Three memory accesses

B Two memory accesses

C Four memory accesses

D One memory access

💡 Hint

Consider the steps: accessing outer page table, inner page table, then the actual data.

Two memory accesses are needed to read the two levels of page tables, plus one to access the actual data, totaling three.

🔍 Analysis

advanced

Calculating page table size in multi-level paging

Given a 32-bit virtual address space with 4 KB page size and a two-level paging scheme where each page table fits exactly in one page, what is the size of each page table?

A 4 KB

B 1 KB

C 2 KB

D 8 KB

💡 Hint

Recall that each page table fits in one page and page size is 4 KB.

Each page table occupies one page, and since the page size is 4 KB, each page table is 4 KB in size.

❓ Comparison

advanced

Difference between single-level and multi-level paging

Which of the following best describes a key difference between single-level and multi-level paging?

A Single-level paging uses multiple page tables, while multi-level paging uses only one.

B Single-level paging supports larger virtual address spaces than multi-level paging.

C Multi-level paging eliminates page faults, but single-level paging does not.

D Multi-level paging reduces memory usage by loading only parts of the page table, while single-level paging requires the entire page table in memory.

💡 Hint

Think about how page tables are stored and accessed in both schemes.

Multi-level paging breaks the page table into smaller parts, loading only needed parts into memory, saving space. Single-level paging requires the full page table in memory.

❓ Reasoning

expert

Impact of multi-level paging on TLB performance

How does multi-level paging typically affect the performance of the Translation Lookaside Buffer (TLB) in a system?

A It increases TLB hit rate by reducing the number of page table entries needed.

B It decreases TLB hit rate because more page table entries must be accessed for address translation.

C It has no effect on TLB performance since TLB caches physical addresses only.

D It requires the TLB to store multiple levels of page table entries separately.

💡 Hint

Consider how multi-level paging changes the number of memory accesses and the TLB's role.

Multi-level paging increases the number of page table entries involved in translation, which can reduce TLB hit rate because more entries must be cached or accessed.

Practice

1. What is the main purpose of multi-level paging in operating systems?

easy

A. To break memory addresses into parts and reduce the size of page tables

B. To increase the size of the physical memory

C. To combine multiple processes into one

D. To speed up the CPU clock

Solution

1. Step 1: Understand the problem of large page tables

   Large memory requires large page tables, which consume a lot of memory.

2. Step 2: Role of multi-level paging

   Multi-level paging breaks addresses into parts and uses multiple smaller page tables to save memory.

3. Final Answer:

   To break memory addresses into parts and reduce the size of page tables -> Option A

4. Quick Check:

   Multi-level paging reduces page table size = C [OK]

Hint: Multi-level paging splits addresses to save memory [OK]

Common Mistakes:

• Thinking it increases physical memory
• Confusing with process combining
• Assuming it speeds CPU clock

2. Which of the following correctly describes the structure of multi-level paging?

easy

A. A single large page table containing all entries

B. Multiple page tables arranged in a hierarchy

C. A flat list of physical addresses

D. A queue of page requests

Solution

1. Step 1: Recall the definition of multi-level paging

   Multi-level paging uses several page tables arranged in levels, not just one big table.

2. Step 2: Identify the correct structure

   The hierarchy of page tables allows efficient address translation and memory use.

3. Final Answer:

   Multiple page tables arranged in a hierarchy -> Option B

4. Quick Check:

   Multi-level paging uses hierarchical page tables = A [OK]

Hint: Multi-level paging uses hierarchical tables, not one big table [OK]

Common Mistakes:

• Choosing a single large page table
• Confusing with flat address lists
• Thinking it uses queues

3. Given a 32-bit virtual address split into 3 parts for a 3-level paging system: 10 bits for level 1, 10 bits for level 2, and 12 bits for offset, how many entries does the level 2 page table have?

medium

A. 512 entries

B. 4096 entries

C. 2048 entries

D. 1024 entries

Solution

1. Step 1: Understand the bit allocation for level 2

   Level 2 uses 10 bits, so number of entries = 2^10.

2. Step 2: Calculate 2 to the power of 10

   2^10 = 1024 entries in the level 2 page table.

3. Final Answer:

   1024 entries -> Option D

4. Quick Check:

   2^10 = 1024 entries [OK]

Hint: Number of entries = 2^(bits for that level) [OK]

Common Mistakes:

• Using offset bits instead of level bits
• Calculating 2^12 or 2^20 incorrectly
• Mixing levels' bit counts

4. A system uses 2-level paging with 10 bits for the first level and 10 bits for the second level. If the page size is 4 KB, what is the total virtual address size in bits? Identify the error in this calculation: 10 + 10 + 12 = 34 bits.

medium

A. The page size bits are counted twice; correct size is 10 + 10 + 12 = 32 bits

B. The page size bits should be 12, so total is 10 + 10 + 12 = 34 bits

C. The page size bits are counted twice; correct size is 10 + 10 + 12 = 34 bits

D. The page size bits are counted twice; correct size is 10 + 10 = 22 bits

Solution

1. Step 1: Understand the components of virtual address size

   Virtual address size = bits for level 1 + bits for level 2 + bits for page offset.

2. Step 2: Calculate page offset bits from page size

   Page size 4 KB = 2^12 bytes, so offset bits = 12.

3. Step 3: Sum bits correctly

   10 (level 1) + 10 (level 2) + 12 (offset) = 32 bits.

4. Step 4: Identify the error

   Counting page size bits twice or misunderstanding system architecture causes confusion; usually total virtual address size is 32 bits.

5. Final Answer:

   The page size bits are counted twice; correct size is 10 + 10 + 12 = 32 bits -> Option A

6. Quick Check:

   Page size bits counted once, total 32 bits [OK]

Hint: Add bits once per part; page size bits = log2(page size) [OK]

Common Mistakes:

• Counting page size bits twice
• Assuming page size bits are 10
• Ignoring page size when calculating address size

5. In a 3-level paging system, if the virtual address is 48 bits and the page size is 4 KB, how many bits are used for each page table index if the bits are evenly divided among the three levels?

hard

A. 10 bits for each level

B. 14 bits for each level

C. 12 bits for each level

D. 16 bits for each level

Solution

1. Step 1: Calculate offset bits from page size

   Page size 4 KB = 2^12 bytes, so offset bits = 12.

2. Step 2: Calculate bits left for page table indices

   Total virtual address bits = 48, subtract offset bits: 48 - 12 = 36 bits for page tables.

3. Step 3: Divide bits evenly among 3 levels

   36 bits / 3 levels = 12 bits per level for page table indices.

4. Final Answer:

   12 bits for each level -> Option C

5. Quick Check:

   (48 - 12) / 3 = 12 bits per level [OK]

Hint: Subtract offset bits, then divide remaining bits by levels [OK]

Common Mistakes:

• Not subtracting offset bits first
• Dividing total bits by levels without offset
• Using wrong page size bits