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Trace the sequence of events when a CPU accesses a virtual address and the TLB results in a miss. What happens next?

easy🧠🧾 Concept Trace Q12 of Q15
Operating Systems - TLB - Translation Lookaside Buffer & Effective Access Time
Trace the sequence of events when a CPU accesses a virtual address and the TLB results in a miss. What happens next?
AThe system consults the page table to find the physical address, updates the TLB, then accesses memory
BThe TLB automatically fetches the missing translation from disk
CThe CPU retries the access until the TLB hits
DThe CPU immediately triggers a page fault and halts execution
Step-by-Step Solution

  1. Step 1: Identify TLB miss consequence

    A TLB miss means the translation is not cached, so the system must look up the page table.

  2. Step 2: Follow the steps

    On a miss, the page table is consulted to get the physical frame number.
    The TLB is updated with this translation for future accesses.
    Then the memory access proceeds using the physical address.

  3. Step 3: Analyze incorrect options

    A: Page fault only occurs if the page is not in memory, not on every TLB miss.
    B: TLB does not fetch from disk; page table lookup is in memory.
    C: CPU does not retry blindly; it performs page table lookup.

  4. Final Answer:

    Option A -> Option A

  5. Quick Check:

    TLB miss triggers page table lookup and TLB update before memory access.
Quick Trick: TLB miss -> page table lookup -> TLB update -> memory access [OK]
Common Mistakes:
MISTAKES
  • Confusing TLB miss with page fault
  • Thinking TLB fetches translations from disk
Trap Explanation:
PITFALL
  • Option A confuses TLB miss with page fault; option B wrongly assumes TLB fetches from disk, which it does not.
Interviewer Note:
CONTEXT
  • Tests candidate's understanding of the address translation flow on TLB miss.
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