Operating Systems - Paging vs Segmentation - Address Translation
In a system combining segmentation with paging, what is the primary performance bottleneck during address translation, and how can it be mitigated?
In a system combining segmentation with paging, what is the primary performance bottleneck during address translation, and how can it be mitigated?
hard⚙️ Functional Understanding Q10 of Q15
Step-by-Step Solution
Solution:
Step 1: Identify address translation steps
Address translation requires first accessing the segment table, then the page table for that segment.Step 2: Recognize performance bottleneck
This double lookup increases translation latency compared to pure paging or segmentation.Step 3: Mitigation strategy
Using a two-level Translation Lookaside Buffer (TLB) caches both segment and page translations to reduce latency.Final Answer:
Option D -> Option DQuick Check:
Double lookup -> two-level TLB reduces delay [OK]
Quick Trick: Double lookup slows translation; two-level TLB speeds it up [OK]
Common Mistakes:
MISTAKES- Confusing fragmentation issues with translation latency
- Assuming segment compaction solves lookup delay
- Misunderstanding page size impact on segment faults
Trap Explanation:
PITFALL- Other options confuse fragmentation or fault frequency with translation performance.
Interviewer Note:
CONTEXT- Tests understanding of address translation overhead in combined segmentation and paging.
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